AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 711

• Manufacturer Part Number: AT32UC3A4128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.8.3.2
Register Name:
Access Type:
Offset:
Reset Value:
• DMAnINT: DMA Channel n Interrupt
• PnINT: Pipe n Interrupt
• HWUPI: Host Wake-Up Interrupt
• HSOFI: Host Start of Frame Interrupt
• RXRSMI: Upstream Resume Received Interrupt
• RSMEDI: Downstream Resume Sent Interrupt
• RSTI: USB Reset Sent Interrupt
32072G–11/2011
DMA7INT
P7INT
31
23
15
7
-
-
This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if the corresponding
DMAnINTE is one (UHINTE register).
This bit is cleared when the UHDMAnSTATUS interrupt source is cleared.
This bit is set when an interrupt is triggered by the endpoint n (UPSTAn). This triggers a USB interrupt if the corresponding pipe
interrupt enable bit is one (UHINTE register).
This bit is cleared when the interrupt source is served.
This bit is set when the host controller is in the suspend mode (SOFE is zero) and an upstream resume from the peripheral is
detected.
This bit is set when the host controller is in the suspend mode (SOFE is zero) and a peripheral disconnection is detected.
This bit is set when the host controller is in the Idle state (USBSTA.VBUSRQ is zero, no VBus is generated).
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
This bit is set when a SOF is issued by the Host controller. This triggers a USB interrupt when HSOFE is one. When using the
host controller in low speed mode, this bit is also set when a keep-alive is sent.
This bit is cleared when the HSOFIC bit is written to one.
This bit is set when an Upstream Resume has been received from the Device.
This bit is cleared when the RXRSMIC is written to one.
This bit set when a Downstream Resume has been sent to the Device.
This bit is cleared when the RSMEDIC bit is written to one.
This bit is set when a USB Reset has been sent to the device.
This bit is cleared when the RSTIC bit is written to one.
Host Global Interrupt Register
DMA6INT
HWUPI
P6INT
30
22
14
6
-
UHINT
Read-Only
0x0404
0x00000000
DMA5INT
HSOFI
P5INT
29
21
13
5
-
DMA4INT
RXRSMI
P4INT
28
20
12
4
-
DMA3INT
RSMEDI
P3INT
27
19
11
3
-
DMA2INT
P2INT
RSTI
26
18
10
2
-
DMA1INT
DDISCI
P1INT
25
17
9
1
-
DCONNI
P0INT
24
16
8
0
-
711