AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 493

• Manufacturer Part Number: AT32UC3A4128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.9.4
Name:
Access Type:
Offset:
Reset Value:
• ACKLAST: ACK Last Master RX Byte
• PECEN: Packet Error Checking Enable
• NBYTES: Number of Data Bytes in Transfer
• VALID: CMDR Valid
• STOP: Send STOP Condition
• START: Send START Condition
• REPSAME: Transfer is to Same Address as Previous Address
32072G–11/2011
VALID
31
23
15
7
-
0: Causes the last byte in master receive mode (when NBYTES has reached 0) to be NACKed. This is the standard way of
ending a master receiver transfer.
1: Causes the last byte in master receive mode (when NBYTES has reached 0) to be ACKed. Used for performing linked
transfers in master receiver mode with no STOP or REPEATED START between the subtransfers. This is needed when more
than 255 bytes are to be received in one single transmission.
0: Causes the transfer not to use PEC byte verification. The PEC LFSR is still updated for every bit transmitted or received.
Must be used if SMBus mode is disabled.
1: Causes the transfer to use PEC. PEC byte generation (if master transmitter) or PEC byte verification (if master receiver) will
be performed.
The number of data bytes in the transfer. After the specified number of bytes have been transferred, a STOP condition is
transmitted if CMDR.STOP is one. In SMBus mode, if PEC is used, NBYTES includes the PEC byte, i.e. there are NBYTES-1
data bytes and a PEC byte.
0: Indicates that CMDR does not contain a valid command.
1: Indicates that CMDR contains a valid command. This bit is cleared when the command is finished.
0: Do not transmit a STOP condition after the data bytes have been transmitted.
1: Transmit a STOP condition after the data bytes have been transmitted.
0: The transfer in CMDR should not commence with a START or REPEATED START condition.
1: The transfer in CMDR should commence with a START or REPEATED START condition. If the bus is free when the
command is executed, a START condition is used. If the bus is busy, a REPEATED START is used.
Only used in 10-bit addressing mode, always write to 0 in 7-bit addressing mode.
Command Register
STOP
30
22
14
6
CMDR
Read/Write
0x0C
0x00000000
START
29
21
13
5
-
REPSAME
SADR[6:0]
28
20
12
4
NBYTES
TENBIT
27
19
11
3
-
26
18
10
2
-
SADR[9:7]
ACKLAST
25
17
9
1
PECEN
READ
24
16
8
0
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