AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 561

• Manufacturer Part Number: AT32UC3A4128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.6.3.9
25.6.3.10
Figure 25-22. Timeguard Operation
32072G–11/2011
Baud Rate
TXEMPTY
TXRDY
Clock
Write
THR
TXD
Multidrop Mode
Transmitter Timeguard
Start
Bit
D0
D1
Figure 25-21. Parity Error
If PAR is either 0x6 or 0x7, the USART runs in Multidrop mode. This mode differentiates data
and address characters. Data has the parity bit zero and addresses have a one. By writing a one
to the Send Address bit (CR.SENDA) the user will cause the next character written to THR to be
transmitted as an address. Receiving a character with a one as parity bit will set PARE.
The timeguard feature enables the USART to interface slow devices by inserting an idle state on
the TXD line in between two characters. This idle state corresponds to a long stop bit, whose
duration is selected by the Timeguard Value field in the Transmitter Timeguard Register
(TTGR.TG). The transmitter will hold the TXD line high for TG bit periods, in addition to the num-
ber of stop bits. As illustrated in
when TG has a non-zero value. If a pending character has been written to THR, the TXRDY bit
will not be set until this characters start bit has been sent. TXEMPTY will remain low until the
timeguard transmission has completed.
D2
Baud Rate
D3
RXRDY
PARE
Clock
Write
RXD
D4
CR
D5
D6
Start
Bit
D7
Parity
D0
Bit
D1
Stop
Bit
D2
TG = 4
D3
Figure
D4
D5
25-22, the behavior of TXRDY and TXEMPTY is modified
Start
D6
Bit
D7
D0
Parity
Bad
Bit
D1
Stop
Bit
D2
D3
D4
D5
RSTSTA = 1
D6
D7
Parity
Bit
Stop
Bit
TG = 4
561