AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 589

• Manufacturer Part Number: AT32UC3A4128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

• SENDA: Send Address
• STTTO: Start Time-out
• STPBRK: Stop Break
• STTBRK: Start Break
• RSTSTA: Reset Status Bits
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32072G–11/2011
TXDIS: Transmitter Disable
TXEN: Transmitter Enable
RXDIS: Receiver Disable
RXEN: Receiver Enable
RSTTX: Reset Transmitter
RSTRX: Reset Receiver
Writing a one to this bit clears CSR.ITER if ISO7816 is enabled in MR.MODE
Writing a zero to this bit has no effect.
Writing a one to this bit will in multidrop mode send the next character written to THR as an address.
Writing a zero to this bit has no effect.
Writing a one to this bit will abort any current time-out count down, and trigger a new count down when the next character has
been received. CSR.TIMEOUT is also cleared.
Writing a zero to this bit has no effect.
Writing a one to this bit will stop the generation of break signal characters, and then send ones for TTGR.TG duration, or at least
12 bit periods. No effect if no break is being transmitted.
Writing a zero to this bit has no effect.
Writing a one to this bit will start transmission of break characters when current characters present in THR and the transmit shift
register have been sent. No effect if a break signal is already being generated.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the following bits in CSR: PARE, FRAME, OVRE, MANERR, LINBE, LINSFE, LINIPE, LINCE,
LINSNRE, and RXBRK.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the transmitter.
Writing a zero to this bit has no effect.
Writing a one to this bit enables the transmitter if TXDIS is zero.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the receiver.
Writing a zero to this bit has no effect.
Writing a one to this bit enables the receiver if RXDIS is zero.
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the transmitter.
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the receiver.
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