AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 832

• Manufacturer Part Number: AT32UC3A4128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.6.6.4
30.6.7
30.6.7.1
32072G–11/2011
MCI Boot Operation Mode
CE-ATA Error Recovery
Boot Procedure, processor mode
CMDR register (CMDR.SPCMD) must be set to three to issue the CE-ATA completion Signal
Disable Command.
Several methods of ATA command failure may occur, including:
Error conditions are expected to happen infrequently. Thus, a robust error recovery mechanism
may be used for each error event. The recommended error recovery procedure after a time-out
is:
If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA com-
mands. However, if the error recovery procedure does not work as expected or there is another
time-out, the next step is to issue GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE
(CMD0) is a hard reset to the device and completely resets all device states.
Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed
again. If the CE-ATA device completes all MMC commands correctly but fails the ATA command
with the ERR bit set in the ATA Status register, no error recovery action is required. The ATA
command itself failed implying that the device could not complete the action requested, how-
ever, there was no communication or protocol failure. After the device signals an error by setting
the ERR bit to one in the ATA Status register, the host may attempt to retry the command.
In boot operation mode, the processor can read boot data from the slave (MMC device) by keep-
ing the CMD line low after power-on before issuing CMD1. The data can be read from either
boot area or user area depending on register setting.
• No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60).
• CRC is invalid for an MMC command or response.
• CRC16 is invalid for an MMC data packet.
• ATA Status register reflects an error by setting the ERR bit to one.
• The command completion signal does not arrive within a host specified time out period.
• Issue the command completion signal disable if IEN was cleared to zero and the
• Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response.
• Issue a software reset to the CE-ATA device using FAST_IO (CMD39).
1. Configure MCI2 data bus width programming SDCBUS Field in the MCI_SDCR regis-
2. Set the bytecount to 512 bytes and the blockcount to the desired number of block, writ-
3. Issue the Boot Operation Request command by writing to the MCI_CMDR register with
4. The BOOT_ACK field located in the MCI_CMDR register must be set to one, if the
RW_MULTIPLE_BLOCK (CMD61) response has been received.
ter. The BOOT_BUS_WIDTH field located in the device Extended CSD register must
be set accordingly.
ing BLKLEN and BCNT fields of the MCI_BLKR Register.
SPCMD field set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data
transfer”.
BOOT_ACK field of the MMC device located in the Extended CSD register is set to
one.
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