AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 383

• Manufacturer Part Number: AT32UC3A4128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.5.1.4
20.5.1.5
20.5.2
20.5.2.1
20.5.2.2
32072G–11/2011
Advanced Operation
Inputs
Output line timings
Pull-up resistor control
Input glitch filter
responding I/O line is driven by the GPIO. When the bit is written to zero, the GPIO does not
drive the line.
The level driven on an I/O line can be determined by writing to the Output Value Register (OVR).
The level on each I/O line can be read through the Pin Value Register (PVR). This register indi-
cates the level of the I/O lines regardless of whether the lines are driven by the GPIO or by an
external component. Note that due to power saving measures, the PVR register can only be
read when GPER is written to one for the corresponding pin or if interrupt is enabled for the pin.
The figure below shows the timing of the I/O line when writing a one and a zero to OVR. The
same timing applies when performing a ‘set’ or ‘clear’ access, i.e., writing a one to the Output
Value Set Register (OVRS) or the Output Value Clear Register (OVRC). The timing of PVR is
also shown.
Figure 20-3. Output Line Timings
Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled
or disabled by writing a one or a zero to the corresponding bit in the Pull-up Enable Register
(PUER). Control of the pull-up resistor is possible whether an I/O line is controlled by a periph-
eral or the GPIO.
Optional input glitch filters can be enabled on each I/O line. When the glitch filter is enabled, a
glitch with duration of less than 1 clock cycle is automatically rejected, while a pulse with dura-
tion of 2 clock cycles or more is accepted. For pulse durations between 1 clock cycle and 2 clock
cycles, the pulse may or may not be taken into account, depending on the precise timing of its
occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 clock cycles, whereas for
a glitch to be reliably filtered out, its duration must not exceed 1 clock cycle. The filter introduces
2 clock cycles of latency.
The glitch filters are controlled by the Glitch Filter Enable Register (GFER). When a bit is written
to one in GFER, the glitch filter on the corresponding pin is enabled. The glitch filter affects only
interrupt inputs. Inputs to peripherals or the value read through PVR are not affected by the
glitch filters.
Write OVR to 1
Write OVR to 0
OVR / I/O Line
CLK_GPIO
PVR
PB Access
PB Access
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