ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 12

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.10.2
3.10.3
3.11
3.11.1
3.12
8331A–AVR–07/11
Accessing 16-bit Registers
Configuration Change Protection
RAMPD Register
EIND - Extended Indirect Register
Accessing 24- and 32-bit Registers
This register is concatenated with the operand to enable direct addressing of the whole data
memory space above 64KB. Together, RAMPD and the operand will form a 24-bit address.
Figure 3-7.
EIND is concatenated with the Z-register to enable indirect jump and call to locations above the
first 128KB (64K words) of the program memory.
Figure 3-8.
The
These registers must be byte-accessed using two read or write operations. 16-bit registers are
connected to the 8-bit bus and a temporary register using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The
low byte is then written into the temporary register. When the high byte of the 16-bit register is
written, the temporary register is copied into the low byte of the 16-bit register in the same clock
cycle.
For a read operation, the low byte of the 16-bit register must be read before the high byte. When
the low byte register is read by the CPU, the high byte of the 16-bit register is copied into the
temporary register in the same clock cycle as the low byte is read. When the high byte is read, it
is then read from the temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously
when reading or writing the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-
bit register during an atomic 16-bit read/write operation. To prevent this, interrupts can be dis-
abled when writing or reading 16-bit registers.
The temporary registers can also be read and written directly from user software.
For 24- and 32-bit registers, the read and write access is done in the same way as described for
16-bit registers, except there are two temporary registers for 24-bit registers and three for 32-bit
registers. The least-significant byte must be written first when doing a write, and read first when
doing a read.
System critical I/O register settings are protected from accidental modification. The SPM instruc-
tion is protected from accidental execution, and the LPM instruction is protected when reading
Bit (Individually)
Bit (D-pointer)
Bit (Individually)
Bit (D-pointer)
AVR
data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations.
The combined RAMPD + K register.
The combined EIND + Z register.
23
7
23
7
RAMPD
EIND
16
0
16
0
15
15
15
7
Atmel AVR XMEGA AU
ZH
0
8
K
7
7
ZL
0
0
0
0
12