ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 182

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.12.7
14.12.8
8331A–AVR–07/11
INTCTRLB – Interrupt Enable Register B
CTRLFCLR/CTRLFSET – Control Register F Clear/Set
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 – ERRINTLVL[1:0]:Timer Error Interrupt Level
These bits enable the timer error interrupt and select the interrupt level as described in
rupts and Programmable Multilevel Interrupt Controller” on page
• Bit 1:0 – OVFINTLVL[1:0]:Timer Overflow/Underflow Interrupt Level
These bits enable the timer overflow/underflow interrupt and select the interrupt level as
described in
• Bit 7:0 – CCxINTLVL[7:0] - Compare or Capture x Interrupt Level:
These bits enable the timer compare or capture interrupt for channel x and select the interrupt
level as described in
This register is mapped into two I/O memory locations, one for clearing (CTRLxCLR) and one for
setting the register bits (CTRLxSET) when written. Both memory locations will give the same
result when read.
The individual status bit can be set by writing a one to its bit location in CTRLxSET, and cleared
by writing a one to its bit location in CTRLxCLR. This allows each bit to be set or cleared without
use of a read-modify-write operation on a single register.
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x07
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
Bit
+0x09
Read/Write
Initial Value
”Interrupts and Programmable Multilevel Interrupt Controller” on page
R/W
CCDINTLVL[1:0]
7
0
R
R
7
–
0
7
–
0
”Interrupts and Programmable Multilevel Interrupt Controller” on page
R/W
R
R
6
0
6
–
0
6
–
0
R/W
R
R
5
–
0
5
–
0
5
CCCINTLVL[1:0]
0
R
4
–
0
4
–
R
0
R/W
4
0
R/W
R
3
0
3
0
Atmel AVR XMEGA AU
R/W
CMD[1:0]
CMD[1:0]
CCBINTLVL[1:0]
3
0
R/W
R
2
0
2
0
R/W
2
0
132.
LUPD
LUPD
R/W
R/W
1
0
1
0
R/W
CCAINTLVL[1:0]
1
0
R/W
R/W
DIR
DIR
0
0
0
0
R/W
0
0
132.
CTRLFCLR
CTRLFSET
INTCTRLB
”Inter-
132.
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