ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 167

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.4
14.5
8331A–AVR–07/11
Clock and Event Sources
Double Buffering
The waveform generator modes use these comparisons to set the waveform period or pulse
width.
A prescaled peripheral clock and events from the event system can be used to control the coun-
ter. The event system is also used as a source to the input capture. Combined with the
quadrature decoding functionality in the event system (QDEC), the timer/counter can be used
for quadrature decoding.
The timer/counter can be clocked from the peripheral clock (clk
Figure 14-3
Figure 14-3. Clock and event selection.
The peripheral clock is fed into a common prescaler (common for all timer/counters in a device).
Prescaler outputs from 1 to 1/1024 are directly available for selection by the timer/counter. In
addition, the whole range of prescaling from 1 to 2
Clock selection (CLKSEL) selects one of the prescaler outputs directly or an event channel as
the counter (CNT) input. This is referred to as normal operation of the counter. For details, refer
to
external clock signal on any I/O pin, may be used as the clock input.
In addition, the timer/counter can be controlled via the event system. The event selection
(EVSEL) and event action (EVACT) settings are used to trigger an event action from one or
more events. This is referred to as event action controlled operation of the counter. For details,
refer to
tion is used, the clock selection must be set to use an event channel as the counter input.
By default, no clock input is selected and the timer/counter is not running.
The period register and the CC registers are all double buffered. Each buffer register has a buf-
fer valid (BV) flag, which indicates that the buffer register contains a valid, i.e. new, value that
can be copied into the corresponding period or CC register. When the period register and CC
channels are used for a compare operation, the buffer valid flag is set when data is written to the
”Normal Operation” on page
clk
”Event Action Controlled Operation” on page
PER
shows the clock and event selection.
CLKSEL
EVACT
EVSEL
Prescaler
Common
{1,2,4,8,64,256,1024}
169. By using the event system, any event source, such as an
(Encoding)
clk /
clk
2
{0,...,15}
PER
/
15
Event System
Atmel AVR XMEGA AU
event channels
times is available through the event system.
169. When event action controlled opera-
PER
) or the event system, and
Control Logic
events
CNT
167