ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 361

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.9.1
28.9.2
28.9.3
8331A–AVR–07/11
Single conversion without gain
Single conversion with gain
Single conversions on two ADC channels
The Most Significant Bit (MSB) of the result is converted first, and the rest of the bits are con-
verted during the next 3 (for 8-bit results) or 5 (for 12-bit results) ADC clock cycles. Converting
one bit takes a half ADC clock period. During the last cycle the result is prepared before the
Interrupt Flag is set. The result is available in the Result Register for readout.
Figure 28-13 on page 361
ing of the start conversion bit, or the event triggering the conversion (START), must occur at
least one peripheral clock cycle before the ADC clock cycle on which the conversion starts (indi-
cated with the grey slope of the START trigger).
The input source is sampled in the first half of the first cycle.
Figure 28-13. ADC timing for one single conversion without gain
Figure 28-14 on page 361
the
sample and amplify the input source before the ADC samples it, and converts the amplified
value. Compared to a single conversion without gain this adds one ADC clock cycle (between
START and ADC Sample) for the gain stage sample and amplify. The sample time for the gain
stage is one half ADC clock cycle.
Figure 28-14. ADC timing for one single conversion with gain
Figure 28-15 on page 362
pipelined design enables the second conversion to start on the next ADC clock cycle after the
GAINSTAGE AMPLIFY
GAINSTAGE SAMPLE
CONVERTING BIT
”Overview” on page 353
CONVERTING BIT
ADC SAMPLE
ADC SAMPLE
CLK
START
CLK
START
ADC
IF
ADC
IF
1
1
MSB
shows the ADC timing for one single conversion with gain. As seen in
shows the ADC timing for a single conversion without gain. The writ-
shows the ADC timing for single conversions on two Channels. The
10
the gain stage is placed prior to the actual ADC. The gainstage will
2
MSB
2
9
10
8
3
9
3
7
8
4
6
7
4
Atmel AVR XMEGA AU
5
6
5
4
5
5
4
3
6
3
2
6
2
1
7
1
LSB
LSB
7
8
8
9
361