ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 362

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.9.4
28.9.5
8331A–AVR–07/11
Single conversions on two ADC channels, CH0 with gain
Single conversions on two ADC channels, CH1 with gain
first conversion has started. In this example both conversions replaced at the same time, but
conversion on ADC Channel 1(CH1) does not start until the ADC samples and performs conver-
sion on MSB on Channel 0 (CH0).
Figure 28-15. ADC timing for single conversions on two ADC channels
Figure 28-16 on page 362
nels where ADC Channel 0 uses the gain stage. As the gain stage introduce one addition cycle
for the gain sample and amplify, the sample for ADC Channel 1 is also delayed one ADC clock
cycle, until the ADC sample and MSB conversion is done for ADC Channel 0.
Figure 28-16. ADC timing for single conversion on two ADC channels, CH0 with gain
Figure 28-17 on page 363
nels where ADC Channel 1 uses the gain stage.
CONVERTING BIT CH0
CONVERTING BIT CH1
CONVERTING BIT CH0
CONVERTING BIT CH1
GAINSTAGE AMPLIFY
START CH1, wo/GAIN
GAINSTAGE SAMPLE
START CH0, w/GAIN
ADC SAMPLE
ADC SAMPLE
START CH0
START CH1
CLK
IF CH0
IF CH1
CLK
IF CH0
IF CH1
ADC
ADC
1
1
MSB
shows the conversion timing for single conversions on two ADC chan-
shows the conversion timing for single conversions on two ADC chan-
10
2
MSB
2
MSB
9
10
3
10
8
MSB
9
3
7
9
10
8
4
6
8
7
9
4
6
8
5
7
5
Atmel AVR XMEGA AU
5
7
4
6
5
4
6
3
5
6
3
5
2
4
6
2
4
1
3
7
1
3
LSB
2
LSB
2
7
8
1
1
LSB
LSB
8
9
10
9
362