ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 19

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4. Memories
4.1
4.2
8331A–AVR–07/11
Features
Overview
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This section describes the different memories in XMEGA AU devices. The AVR architecture has
two main memory spaces, the program memory and the data memory. Executable code can
reside only in the program memory, while data can be stored in the program memory and the
data memory. The data memory includes the internal SRAM EEPROM for nonvolatile data stor-
age. All memory spaces are linear and require no memory bank switching. Nonvolatile memory
Flash program memory
Data memory
Production signature row memory for factory programmed data
User signature row
– One linear address space
– In-system programmable
– Self-programming and boot loader support
– Application section for application code
– Application table section for application code or data storage
– Boot section for application code or bootloader code
– Separate read/write protection lock bits for all sections
– Built in fast CRC check of a selectable flash program memory section
– One linear address space
– Single-cycle access from CPU
– SRAM
– EEPROM
– I/O memory
– External memory support
– Bus arbitration
– Separate buses for SRAM, EEPROM, I/O memory, and external memory access
Byte and page accessible
Optional memory mapping for direct load and store
Configuration and status registers for all peripherals and modules
16 bit-accessible general purpose registers for global variables or flags
SRAM
SDRAM
Memory mapped external hardware
Safe and deterministic handling of priority between CPU, DMA controller, and other bus
masters
Simultaneous bus access for CPU and DMA controller
ID for each microcontroller device type
Serial number for each device
Calibration bytes for factory calibrated peripherals
One flash page in size
Can be read and written from software
Content is kept after chip erase
Atmel AVR XMEGA AU
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