ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 173

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.7.3
14.7.4
14.7.5
14.8
8331A–AVR–07/11
Compare Channel
Pulse Width Capture
32-bit Input Capture
Capture Overflow
Selecting the pulse width measure event action makes the enabled compare channel perform
the input capture action on falling edge events and the restart action on rising edge events. The
counter will then restart on positive edge events, and the input capture will be performed on the
negative edge event. The event source must be an I/O pin, and the sense configuration for the
pin must be set to generate an event on both edges.
example where the pulse width is measured twice for an external signal.
Figure 14-13. Pulse width capture of an external signal.
Two timer/counters can be used together to enable true 32-bit input capture. In a typical 32-bit
input capture setup, the overflow event of the least-significant timer is connected via the event
system and used as the clock input for the most-significant timer.
The most-significant timer will be updated one peripheral clock period after an overflow occurs
for the least-significant timer. To compensate for this, the capture event for the most-significant
timer must be equally delayed by setting the event delay bit for this timer.
The timer/counter can detect buffer overflow of the input capture channels. When both the buffer
valid flag and the capture interrupt flag are set and a new capture event is detected, there is
nowhere to store the new timestamp. If a buffer overflow is detected, the new value is rejected,
the error interrupt flag is set, and the optional interrupt is generated.
Each compare channel continuously compares the counter value (CNT) with the CCx register. If
CNT equals CCx, the comparator signals a match. The match will set the CC channel's interrupt
flag at the next timer clock cycle, and the event and optional interrupt are generated.
The compare buffer register provides double buffer capability equivalent to that for the period
buffer. The double buffering synchronizes the update of the CCx register with the buffer value to
either the TOP or BOTTOM of the counting sequence according to the UPDATE condition. The
external signal
events
CNT
BOTTOM
MAX
Pulsewitdh (t
p
)
Atmel AVR XMEGA AU
Figure 14-13 on page 173
"capture"
shows and
173