ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 123

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.6
10.6.1
8331A–AVR–07/11
Register Description
CTRL: Control Register
• Bit 7: 6 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 5 – HIGHESR: High ESR Mode
Setting this bit will increase the current used to drive the crystal and increase the swing on the
TOSC2 pin. This allows use of crystals with higher load and higher ESR.
• Bit 4 – XOSCSEL: Crystal Oscillator Output Selection
This bit selects the prescaled clock output from the 32.768kHz crystal oscillator. After reset, this
bit is zero, and the 1Hz clock output is used as input for the RTC. Setting this bit will select the
1.024kHz clock output as input for the RTC32. This bit cannot be changed when XOSCEN is
set.
• Bit 3 – XOSCEN: Crystal Oscillator Enable
Setting this bit will enable the 32.768kHz crystal oscillator. Writing the bit to zero will have no
effect, and the oscillator will remain enabled until a battery backup reset is issued.
• Bit 2 – XOSCFDEN: Crystal Oscillator Failure Detection Enable
Setting this bit will enable the crystal oscillator monitor. The monitor will detect if the crystal is
stopped or loses connection temporarily. At least 64 swings must be lost before the failure
detection is triggered. Writing the bit to zero will have no effect, and the crystal oscillator monitor
will remain enabled until a battery backup reset is issued.
• Bit 1 – ACCEN: Module Access Enable
Setting this bit will enable access to the battery backup registers. After main reset, this bit must
be set in order to access (read from and write to) the battery backup registers, except for the
BBPODF, the BBBODF, and the BBPWR flags, which are always accessible. Writing this bit to
zero will have no effect; only a device reset will clear this bit.
• Bit 0 – RESET: Reset
Setting this bit will force a reset of the battery backup system lasting one peripheral clock cycle.
Writing the bit to zero will have no effect. Writing a one to XOSCEN or XOSCFDEN at the same
time will block writing to this bit. When this bit is set, HIGHESR, XOSCSEL, XOSCEN, and
XOSCFDEN in CTRL and XOSCRDY in STATUS will be cleared.
Bit
+0x00
Read/Write
initial Value
R
7
0
–
R
6
–
0
HIGHESR
R/W
5
0
XOSCSEL
R/W
4
0
XOSCEN
R/W
3
0
Atmel AVR XMEGA AU
XOSCFDEN
R/W
2
0
ACCEN
R/W
1
0
RESET
R/W
0
0
CTRL
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