ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 152

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.13.12 INT1MASK – Interrupt 1 Mask Register
13.13.13 INTFLAGS – Interrupt Flag Register
13.13.14 REMAP – Pin Remap Register
8331A–AVR–07/11
• Bit 7:0 – INT0MSK[7:0]: Interrupt 0 Mask Register
These bits are used to mask which pins can be used as sources for port interrupt 0. If
INT0MASKn is written to one, pin n is used as source for port interrupt 0.The input sense config-
uration for each pin is decided by the PINnCTRL registers.
• Bit 7:0 – INT1MASK[7:0]: Interrupt 1 Mask Register
These bits are used to mask which pins can be used as sources for port interrupt 1. If
INT1MASKn is written to one, pin n is used as source for port interrupt 1.The input sense config-
uration for each pin is decided by the PINnCTRL registers.
• Bit 7:2 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1:0 – INTnIF: Interrupt n Flag
The INTnIF flag is set when a pin change/state matches the pin's input sense configuration, and
the pin is set as source for port interrupt n. Writing a one to this flag's bit location will clear the
flag. For enabling and executing the interrupt, refer to the interrupt level description.
The pin remap functionality is available for PORTC - PORTF only
• Bit 7:6 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 5 – SPI: SPI Remap
Setting this bit to one will swap the pin locations of the SCK and MOSI pins to have pin compati-
bility between SPI and USART when the USART is operating as a SPI master.
Bit
+0x0B
Read/Write
Initial Value
Bit
+0x0C
Read/Write
Initial Value
Bit
+0x0E
Read/Write
Initial Value
R/W
7
0
7
–
R
0
7
–
R
0
R/W
6
0
6
–
R
0
6
–
R
0
R/W
R/W
SPI
R
5
0
5
–
0
5
0
USART0
R/W
R/W
R
4
0
4
–
0
4
0
INT1MSK[7:0]
TC0D
R/W
R/W
Atmel AVR XMEGA AU
R
3
0
3
–
0
3
0
TC0C
R/W
R/W
R
2
0
2
–
0
2
0
INT1IF
TC0B
R/W
R/W
R/W
1
0
1
0
1
0
INT0IF
TC0A
R/W
R/W
R/W
0
0
0
0
0
0
INT1MASK
INTFLAGS
REMAP
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