LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 38

• Manufacturer Part Number: LPC2926_27_29
• Description: The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2926_27_29
Product data sheet
6.14.3.1 Pin description
6.15.1 Functional description
6.15 Modulation and sampling control subsystem
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The main features if the I
Table 22.
[1]
The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2926/2927/2929
includes four Pulse Width Modulators (PWMs), three 10-bit successive approximation
Analog-to-Digital Converters (ADCs) and two timers.
The key features of the MSCSS are:
The MSCSS contains Pulse Width Modulators (PWMs), Analog-to-Digital Converters
(ADCs) and timers.
Symbol
I2C SCL0/1
I2C SDA0/1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
I
not support powering off of individual devices connected to the same bus lines.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
All I
Note that the pins are not I
Two 10-bit, 400 ksample/s, 8-channel ADCs with 3.3 V inputs and various trigger-
start options
One 10-bit, 400 ksample/s, 8-channel ADC with 5 V inputs (5 V measurement range)
and various trigger-start options
Four 6-channel PWMs (Pulse Width Modulators) with capture and trap functionality
Two dedicated timers to schedule and synchronize the PWMs and ADCs
Quadrature encoder interface
2
C0/1 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I
2
C-bus controllers support multiple address recognition and a bus monitor mode.
2
C-bus can be used for test and diagnostic purposes.
I
2
C-bus pins
Pin name
SCL0/1
SDA0/1
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 28 September 2010
[1]
2
2
C-bus interfaces are:
C-bus compliant open-drain pins.
Direction
I/O
I/O
ARM9 microcontroller with CAN, LIN, and USB
Description
I2C clock input/output
I2C data input/output
LPC2926/2927/2929
2
C is a multi-master bus, and it can be
© NXP B.V. 2010. All rights reserved.
2
C-bus) and do
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