LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 42

• Manufacturer Part Number: LPC2926_27_29
• Description: The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2926_27_29
Product data sheet
Fig 9.
APB system bus
ADC block diagram
IRQ compare
6.15.4.1 Functional description
6.15.4.2 Pin description
IRQ scan
The ADC block diagram,
functionality is divided into two major parts; one part running on the MSCSS Subsystem
clock, the other on the ADC clock. This split into two clock domains affects the behavior
from a system-level perspective. The actual analog-to-digital conversions take place in the
ADC clock domain, but system control takes place in the system clock domain.
A mechanism is provided to modify configuration of the ADC and control the moment at
which the updated configuration is transferred to the ADC domain.
The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower
than or equal to the system clock frequency. To meet this constraint or to select the
desired lower sampling frequency, the clock generation unit provides a programmable
fractional system-clock divider dedicated to the ADC clock. Conversion rate is determined
by the ADC clock frequency divided by the number of resolution bits plus one. Accessing
ADC registers requires an enabled ADC clock, which is controllable via the clock
generation unit, see
Each ADC has four start inputs. Note that start 0 and start 2 are captured in the system
clock domain while start 1 and start 3 are captured in the ADC domain. The start inputs
are connected at MSCSS level, see
The three ADC modules in the MSCSS have the pins described below. The ADCx input
pins are combined with other functions on the port pins of the LPC2926/2927/2929. The
VREFN and VREFP pins are common to all ADCs.
start 0
system clock
REGISTERS
CONTROL
ADC
AND
start 2
SYSTEM DOMAIN
configuration data
conversion data
All information provided in this document is subject to legal disclaimers.
update
IRQ
Section
Rev. 5 — 28 September 2010
Figure
6.16.2.
start 1
(up to 4.5 MHz)
REGISTERS
CONTROL
ADC clock
9, shows the basic architecture of each ADC. The ADC
ADC
AND
Section 6.15
start 3
ARM9 microcontroller with CAN, LIN, and USB
sync_out
3.3 V
ADC DOMAIN
LPC2926/2927/2929
ADC1/2
3.3 V
for details.
Table 23
ADC0
5 V
ANALOG
ANALOG
3.3 V IN
5 V IN
MUX
MUX
shows the ADC pins.
© NXP B.V. 2010. All rights reserved.
ADC0 IN[7:0]
ADC1 IN[7:0]
ADC2 IN[7:0]
002aae360
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