LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 56

• Manufacturer Part Number: LPC2926_27_29
• Description: The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2926_27_29
Product data sheet
6.16.4.1 Functional description
Each reset output is defined as a combination of reset input sources including the external
reset input pins and internal power-on reset, see
this table form a sort of cascade to provide the multiple levels of impact that a reset may
have. The combined input sources are logically OR-ed together so that activating any of
the listed reset sources causes the output to go active.
Table 30.
Reset output
POR_RST
RGU_RST
PCR_RST
COLD_RST
WARM_RST
SCU_RST
CFID_RST
FMC_RST
EMC_RST
SMC_RST
GESS_A2V_RST
PESS_A2V_RST
GPIO_RST
UART_RST
TMR_RST
SPI_RST
IVNSS_A2V_RST
IVNSS_CAN_RST
IVNSS_LIN_RST
MSCSS_A2V_RST
MSCSS_PWM_RST
MSCSS_ADC_RST
MSCSS_TMR_RST
I2C_RST
QEI_RST
DMA_RST
USB_RST
VIC_RST
AHB_RST
•
•
•
Automatic reset stretching and release
Monitor function to trace resets back to source
Register write-protection mechanism to prevent unintentional resets
Reset output configuration
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 28 September 2010
Reset source
power-on reset module
POR_RST, RST pin
RGU_RST, WATCHDOG PCR internal; is source for COLD_RST
PCR_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
ARM9 microcontroller with CAN, LIN, and USB
all CAN modules including Acceptance filter
all LIN modules
all timer modules in MSCSS
Quadrature encoder
Parts of the device reset when activated
LP_OSC; is source for RGU_RST
RGU internal; is source for PCR_RST
parts with COLD_RST as reset source below
parts with WARM_RST as reset source below
SCU
CFID
embedded Flash Memory Controller (FMC)
embedded SRAM-Memory Controller
external Static Memory Controller (SMC)
GeSS AHB-to-APB bridge
PeSS AHB-to-APB bridge
all GPIO modules
all UART modules
all timer modules in PeSS
all SPI modules
IVNSS AHB-to-APB bridge
MSCSS AHB to APB bridge
all PWM modules
all ADC modules
all I2C modules
GPDMA controller
USB controller
Vectored Interrupt Controller (VIC)
CPU and AHB Bus infrastructure
LPC2926/2927/2929
Table
30. The first five resets listed in
© NXP B.V. 2010. All rights reserved.
56 of 95