ST72321AR6-Auto STMicroelectronics, ST72321AR6-Auto Datasheet - Page 133

• Manufacturer Part Number: ST72321AR6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
14.8.3
Note:
Table 68.
Data I/O register (SPIDR)
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
SPIDR
Bit
4
3
2
1
0
7
MODF
Name
SOD
SSM
SSI
-
SPICSR register description (continued)
Mode Fault flag
Reserved, must be kept cleared
SPI Output Disable
SS Management
SS Internal Mode
This bit is set by hardware when the SS pin is pulled low in master mode (see
Master mode fault (MODF) on page
SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An
access to the SPICR register while MODF = 1 followed by a write to the SPICR
register).
0: No master mode fault detected
1: A fault in master mode has been detected
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode).
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See
page
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin
free for general-purpose I/O)
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the
level of the SS slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
6
123.
5
Doc ID 13829 Rev 1
4
D[7:0]
RW
Function
128). An SPI interrupt can be generated if
3
Serial peripheral interface (SPI)
2
Slave select management on
Reset value: Undefined
1
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