ST72321AR6-Auto STMicroelectronics, ST72321AR6-Auto Datasheet - Page 143

• Manufacturer Part Number: ST72321AR6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
Note:
Note:
Conventional baud rate generation
The baud rate for the receiver and transmitter (Rx and Tx) are set independently and
calculated as follows:
with:
All these bits are in the SCIBRR register.
Example: If f
receive baud rates are 38400 baud.
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
Extended baud rate generation
The extended prescaler option provides a very fine tuning of the baud rate, using a 255
value prescaler, whereas the conventional baud rate generator retains industry standard
software compatibility.
The extended baud rate generator block diagram is described in the
The output clock rate sent to the transmitter or to the receiver is the output from the 16
divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR
register.
The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as follows:
with:
Receiver muting and wake-up feature
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant SCI
service overhead for all non-addressed receivers.
The non-addressed devices may be placed in sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in sleep mode:
●
●
A muted receiver may be awakened by one of the following two ways:
●
●
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits)
ETPR = 1,..,255 (see SCIETPR register)
ERPR = 1,..,255 (see SCIERPR register)
All the reception status bits cannot be set.
All the receive interrupts are inhibited.
by Idle Line detection if the WAKE bit is reset
by Address Mark detection if the WAKE bit is set
CPU
is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and
Tx =
16
Tx =
*
ETPR
Doc ID 13829 Rev 1
(16
f
CPU
*
*
f
(PR
PR)
CPU
*
*
TR)
TR
Rx =
Rx =
Serial communications interface (SCI)
16
(16
*
ERPR
*
f
PR)
CPU
f
CPU
*
RR
*
(PR
*
RR)
Figure
64.
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