ST72321AR6-Auto STMicroelectronics, ST72321AR6-Auto Datasheet - Page 80

• Manufacturer Part Number: ST72321AR6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

Watchdog timer (WDG)
10.5
10.6
10.7
10.8
80/243
Low power modes
Table 35.
Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to the option byte description in
Flash configuration on page
Using Halt mode with the WDG (WDGHALT option)
The following recommendation applies if Halt mode is used when the watchdog is enabled:
Before executing the HALT instruction, refresh the WDG counter to avoid an unexpected
WDG reset immediately after waking up the microcontroller.
Interrupts
None.
Mode
Slow
Wait
Halt
No effect on Watchdog
No effect on Watchdog
OIE bit in
MCCSR
register
Effect of low power modes on WDG
0
0
1
WDGHALT
Option
bit in
Byte
0
1
x
223.
Doc ID 13829 Rev 1
No Watchdog reset is generated. The MCU enters Halt mode.
The Watchdog counter is decremented once and then stops
counting and is no longer able to generate a watchdog reset
until the MCU receives an external interrupt or a reset.
If an external interrupt is received, the Watchdog restarts
counting after 256 or 4096 CPU clocks. If a reset is generated,
the Watchdog is disabled (reset state) unless Hardware
Watchdog is selected by option byte. For application
recommendations see
A reset is generated.
No reset is generated. The MCU enters Active Halt mode. The
Watchdog counter is not decremented. It stop counting. When
the MCU receives an oscillator interrupt or external interrupt,
the Watchdog restarts counting immediately. When the MCU
receives a reset the Watchdog restarts counting after 256 or
4096 CPU clocks.
Effect
Section 10.7
below.
ST72321xx-Auto
Section 21.1.1: