ST72321AR6-Auto STMicroelectronics, ST72321AR6-Auto Datasheet - Page 159

• Manufacturer Part Number: ST72321AR6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
Note:
16.4.2
Closing slave communication
After the last data byte is transferred, a Stop Condition is generated by the master. The
interface detects this condition and sets:
●
Then the interface waits for a read of the SR2 register (see
EV4).
Error cases
●
●
In case of errors, the SCL line is not held low; however, the SDA line can remain low if the
last bits transmitted are all 0. While AF = 1, the SCL line may be held low due to SB or BTF
flags that are set at the same time. It is then necessary to release both lines by software.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released
after the transfer of the current byte.
SMBus compatibility
The ST7 I
modes, SMBus bus protocols and CRC-8 packet error checking. Refer to SMBus Slave
Driver For ST7 I
Master mode
To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent:
●
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address, holding the SCL line low (see
EV5).
EVF and STOPF bits with an interrupt if the ITE bit is set.
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop then the interface discards the data, released the lines and waits for
another Start condition.
If it is a Start then the interface discards the data and waits for the next slave address
on the bus.
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with
an interrupt if the ITE bit is set.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set.
2
C is compatible with the SMBus V1.1 protocol. It supports all SMBus addressing
2
C Peripheral (AN1713).
Doc ID 13829 Rev 1
Figure 68: Transfer sequencing
Figure 68: Transfer sequencing
I2C bus interface (I2C)
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