ST72321AR6-Auto STMicroelectronics, ST72321AR6-Auto Datasheet - Page 149

• Manufacturer Part Number: ST72321AR6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
15.7.2
Control register 1 (SCICR1)
Table 74.
SCICR1
Bit
7
6
5
4
3
2
1
RW
R8
7
WAKE
Name
SCID
PCE
PS
R8
T8
M
SCICR1 register description
Wake-up method
Parity control enable
Parity selection
Receive data bit 8
Transmit data bit 8
Disabled for low power consumption
Word length
RW
T8
This bit is used to store the 9th bit of the received word when M = 1.
This bit is used to store the 9th bit of the transmitted word when M = 1.
When this bit is set the SCI prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption.This bit is set and
cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: The M bit must not be modified during a data transfer (both transmission and
reception).
This bit determines the SCI wake-up method. It is set or cleared by software.
0: Idle line
1: Address mark
This bit selects the hardware parity control (generation and detection). When the
parity control is enabled, the computed parity is inserted at the MSB position (9th
bit if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is
set and cleared by software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
0: Parity control disabled
1: Parity control enabled
This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity is selected after
the current byte.
0: Even parity
1: Odd parity
6
SCID
RW
5
Doc ID 13829 Rev 1
RW
M
4
Function
WAKE
RW
Serial communications interface (SCI)
3
PCE
RW
2
Reset value: X000 0000 (x0h)
RW
PS
1
PIE
RW
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0