CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet
CM68HC05C4ACFB
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CM68HC05C4ACFB Summary of contents
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MC68HC05C4A MC68HCL05C4A MC68HSC05C4A General Release Specification HC05C4AGRS/D REV. 4.0 August 5, 1997 CSIC System Design Group Austin, Texas ...
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General Release Specification Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or ...
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General Release Specification — MC68HC05C4A Section 1. General Description . . . . . . . . . . . . . . 15 Section 2. Memory . . . . . . . . . . . . . ...
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List of Sections General Release Specification 4 List of Sections MC68HC05C4A Rev. 4.0 — MOTOROLA ...
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General Release Specification — MC68HC05C4A 1.1 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 2.1 2.2 2.3 2.4 2.5 3.1 3.2 3.3 3.3.1 3.3.2 MC68HC05C4A Rev. 4.0 — MOTOROLA Section 1. General Description Contents ...
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Table of Contents 3.3.3 3.3.4 3.3.5 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 5.1 5.2 5.3 5.4 5.5 5.5.1 5.5.2 5.5.3 5.5.4 6.1 6.2 6.3 6.4 6.5 7.1 7.2 7.3 7.4 General Release Specification 6 Program Counter ................................................................ 33 ...
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MC68HC05C4A Rev. 4.0 — MOTOROLA Port C........................................................................................50 Port D........................................................................................51 ...
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Table of Contents 10.4.3 10.4.4 10.5 10.6 10.6.1 10.6.2 10.6.3 11.1 11.2 11.3 11.4 11.4.1 11.4.2 12.1 12.2 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.5 12.6 General Release Specification 8 Serial ...
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V Control Timing ...............................................................123 13.11 5.0 V Serial Peripheral Interface Timing .................................126 13.12 3.3 V Serial Peripheral Interface Timing .................................127 14.1 14.2 14.3 14.4 14.5 14.6 15.1 15.2 15.3 ...
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Table of Contents A.1 A.2 A.3 A.4 A.5 A.6 B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 C.1 C.2 General Release Specification 10 Appendix A. MC68HCL05C4A Contents................................................................................. 141 Introduction ............................................................................ 141 Low-Power Operating Temperature Range ........................... 141 2.5–3 ...
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General Release Specification — MC68HC05C4A Figure 1-1 1-2 1-3 1-4 1-5 2-1 2-2 3-1 3-2 4-1 6-1 6-2 7-1 7-2 8-1 8-2 8-3 8-4 8-5 9-1 9-2 9-3 MC68HC05C4A Rev. 4.0 — MOTOROLA Title Block Diagram . . . . ...
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List of Figures Figure 9-4 9-5 9-6 9-7 9-8 10-1 10-2 10-3 10-4 10-5 11-1 11-2 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 General Release Specification 12 Title SCI Data Register (SCDR ...
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General Release Specification — MC68HC05C4A Table 4-1 7-1 9-1 9-2 9-3 10-1 Serial Peripheral Rate Selection .88 11-1 ...
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List of Tables General Release Specification 14 List of Tables MC68HC05C4A Rev. 4.0 — MOTOROLA ...
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General Release Specification — MC68HC05C4A 1.1 Contents 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.2 Introduction The MC68HC05C4A is an enhanced version of the MC68HC05C4. It includes keyboard scanning logic, a high-current pin, ...
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General Description 1.3 Features • • • • • • • • • • • • • • • • • • • • General Release Specification 16 M68HC05 Core Single 3.0- to 5.5-Volt Supply Available Packages: – 40-Pin Dual ...
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USER ROM AND USER VECTORS — 4160 BYTES SELF-CHECK ROM — 240 BYTES IRQ CPU RESET CONTROL CPU REGISTERS CONDITION CODE REGISTER OSC2 OSCILLATOR OSC1 COP SYSTEM V DD POWER Port B pins ...
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General Description 1.4 Mask Options Eight mask options are available to select the pullup/interrupts on port pin-by-pin basis. There are also four mask options for: 1. IRQ, edge-sensitive only or edge- and level-sensitive 2. CLOCK, crystal or ...
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MC68HC05C4A Rev. 4.0 — MOTOROLA 1 RESET 2 IRQ 3 NC* 4 PA7 5 PA6 6 PA5 7 PA4 8 PA3 9 PA2 PA1 10 PA0 11 PB0 12 13 PB1 14 PB2 PB3 15 16 PB4 PB5 17 PB6 ...
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General Description General Release Specification 20 RESET 1 IRQ 2 NC* 3 PA7 4 PA6 5 PA5 6 PA4 7 PA3 8 PA2 9 PA1 10 PA0 11 PB0 12 PB1 13 PB2 14 PB3 PB4 17 ...
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MC68HC05C4A Rev. 4.0 — MOTOROLA PA5 7 PA4 8 9 PA3 PA2 10 11 PA1 PA0 12 13 PB0 14 PB1 PB2 15 PB3 16 PB4 MC68HC705C4A OTPs are to be used in the same application, this ...
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General Description 1.5.1 V and Power is supplied to the microcontroller using these two pins. V positive supply and V 1.5.2 IRQ This pin has a mask selectable option that provides two different choices of interrupt triggering ...
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Port A (PA0–PA7) These eight input/output (I/O) lines comprise port A. The state of any pin is software programmable and all port A lines are configured as input during power-on or reset. For detailed information on I/O programming, see ...
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General Description General Release Specification 24 General Description MC68HC05C4A Rev. 4.0 — MOTOROLA ...
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General Release Specification — MC68HC05C4A 2.1 Contents 2.2 2.3 2.4 2.5 2.2 Introduction The MC68HC05C4A has an 8-Kbyte memory map, consisting of user read-only memory (ROM), user random-access memory (RAM), self- check ROM, and input/output (I/O) registers. See Figure 2.3 ...
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Memory 2.4 ROM Security Feature A security help prevent externally reading of code in the ROM. This feature aids in keeping customer-developed software proprietary. 2.5 Random-Access Memory (RAM) The user RAM consists of 176 bytes and is used both for ...
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I/O REGISTERS 32 BYTES $001F $0020 USER ROM 48 BYTES $004F $0050 RAM 176 BYTES $00BF $00C0 STACK 64 BYTES $00FF $0100 USER ROM 4096 BYTES $10FF $1100 UNUSED 3548 BYTES $1EFF $1F00 SELF-CHECK ROM AND VECTORS 240 BYTES ...
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Memory Addr. Register Port A Data $0000 PORTA Port B Data $0001 PORTB Port C Data $0002 PORTD Port D Data $0003 PORTD Port A Data Direction $0004 DDRA Port B Data Direction $0005 DDRB Port C Data Direction $0006 ...
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Addr. Register SCI Baud Rate Register $000D BAUD SCI Control 1 $000E SCCR1 SCI Control 2 $000F SCCR2 SCI Status Register $0010 SCSR SCI Data Register $0011 SCDAT Timer Control Register $0012 TCR Timer Status Register $0013 TSR Input Capture ...
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Memory Addr. Register Alternate Counter Register $001A ALTCNT (High) Alternate Counter Register $001B ALTCNT (Low) $001C Unimplemented $001D Unimplemented $001E Unimplemented $001F Reserved $1FF0 COP Reset Figure 2-2. Input/Output Registers (Continued) General Release Specification 30 Bit Read: ...
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General Release Specification — MC68HC05C4A 3.1 Contents 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.2 Introduction This section describes the CPU registers. 3.3 CPU Registers The five CPU registers are shown in stacking order is shown in MC68HC05C4A Rev. 4.0 ...
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Central Processor Unit (CPU) 3.3.1 Accumulator The accumulator (A) shown in register used to hold operands and results of arithmetic calculations or data manipulations. 3.3.2 Index Register The index register ( 8-bit register used by the indexed addressing ...
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Program Counter The program counter (PC 13-bit register that contains the address of the next byte to be fetched. 3.3.4 Stack Pointer The stack pointer (SP) contains the address of the next free location on the stack. ...
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Central Processor Unit (CPU) N — Negative When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Z — Zero When set, this bit indicates that the result of the last arithmetic, ...
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General Release Specification — MC68HC05C4A 4.1 Contents 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.2 Introduction The MCU can be interrupted five different ways: • • Port B interrupts, if enabled, are combined with the IRQ to form a single ...
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Interrupts Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but they are considered pending until the current instruction is complete. NOTE: The current instruction is the one already fetched and being operated on. When ...
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Hardware Controlled Interrupt Sequence Three functions (RESET, STOP, and WAIT) are not in the strictest sense interrupts; however, they are acted upon in a similar manner. Flowcharts for hardware interrupts are shown in 1. RESET — A low input ...
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Interrupts Y RESTORE REGISTERS FROM STACK: CCR General Release Specification 38 FROM RESET I BIT IN CCR SET? N IRQ Y CLEAR IRQ EXTERNAL INTERRUPT REQUEST LATCH ? N Y INTERNAL TIMER INTERRUPT ? N Y INTERNAL ...
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External Interrupt (IRQ) If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge ...
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Interrupts 4.8 Serial Peripheral Interrupt (SPI) Two different SPI interrupt flags cause an SPI interrupt whenever they are set and enabled. The interrupt flags are in the SPI status register (SPSR), and the enable bits are in the SPI control ...
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General Release Specification — MC68HC05C4A 5.1 Contents 5.2 5.3 5.4 5.5 5.5.1 5.5.2 5.5.3 5.5.4 5.2 Introduction The MCU can be reset three ways: 1. Initial power-on reset function 2. Active low input to the RESET pin 3. Computer operating ...
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Resets 5.3 Power-On Reset (POR) An internal reset is generated on power-up to allow the internal clock generator to stabilize. The power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the ...
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COP During Wait Mode The COP will continue to operate normally during wait mode. The software should pull the device out of wait mode periodically and reset the COP by writing to the COPC bit to prevent a COP ...
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Resets General Release Specification 44 MC68HC05C4A Resets Rev. 4.0 — MOTOROLA ...
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General Release Specification — MC68HC05C4A 6.1 Contents 6.2 6.3 6.4 6.5 6.2 Introduction This section describes the two low-power modes — stop and wait. Figure 6-1 WAIT instructions. MC68HC05C4A Rev. 4.0 — MOTOROLA Section 6. Low-Power Modes Introduction ...............................................................................45 Stop ...
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Low-Power Modes STOP STOP OSCILLATOR AND ALL CLOCKS CLEAR I BIT N RESET EXTERNAL INTERRUPT (IRQ TURN ON OSCILLATOR WAIT FOR TIME DELAY TO STABILIZE 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I ...
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All input/output lines remain unchanged. The processor can be brought out of stop mode only by an external interrupt or reset. 6.4 Stop Recovery The processor can be brought out of stop mode only by an external interrupt or ...
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Low-Power Modes General Release Specification 48 Low-Power Modes MC68HC05C4A Rev. 4.0 — MOTOROLA ...
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General Release Specification — MC68HC05C4A 7.1 Contents 7.2 7.3 7.4 7.5 7.6 7.7 7.2 Introduction The MC68HC05C4A has three 8-bit input/output (I/O) ports.These 24 port pins are programmable as either inputs or outputs under software control of the data direction ...
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Input/Output (I/O) Ports 7.4 Port B Port 8-bit bidirectional port. The port B data register is at $0001, and the data direction register (DDR $0005. Reset does not affect the data registers, but clears the ...
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Port D Port 7-bit fixed input port. Four of its pins are shared with the SPI subsystem, and two more are shared with the SCI subsystem. Reset does not affect the data registers. During reset, all ...
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Input/Output (I/O) Ports [1] This output buffer enables the latched output to drive the pin when DDR bit is 1 (output mode). [2] This input buffer is enabled when DDR bit is 0 (input mode). [3] This input buffer is ...
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General Release Specification — MC68HC05C4A 8.1 Contents 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.2 Introduction The timer consists of a 16-bit, software-programmable counter driven by a fixed divide-by-four prescaler. This timer can be used for many purposes, including ...
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Timer HIGH LOW BYTE BYTE OUTPUT $16 COMPARE $17 REGISTER OUTPUT COMPARE CIRCUIT TIMER ICF OCF TOF STATUS REGISTER INTERRUPT CIRCUIT General Release Specification 54 INTERNAL BUS INTERNAL PROCESSOR 8-BIT CLOCK BUFFER 4 HIGH BYTE HIGH LOW BYTE BYTE INPUT ...
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Counter The key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2.0 microseconds if ...
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Timer 8.4 Output Compare Register The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB) and $17 (LSB). The output compare register is used for several purposes, such as indicating when a period of ...
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OUTPUT COMPARE REGISTER HIGH OUTPUT COMPARE REGISTER LOW 8.5 Input Capture Register Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the ...
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Timer the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($15) does not inhibit the free- running counter transfer, ...
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ICIE — Input Capture Interrupt Enable OCIE — Output Compare Interrupt Enable TOIE — Timer Overflow Interrupt Enable IEDG — Input Edge Value of input edge determines which level transition on TCAP pin will trigger free-running counter transfer to the ...
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Timer 8.7 Timer Status Register The TSR is a read-only register containing three status flag bits. Address: Read: Write: Reset: ICF — Input Capture Flag OCF — Output Compare Flag TOF — Timer Overflow Flag Bits 0–4 — Not used ...
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A problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. Without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. ...
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Timer General Release Specification 62 MC68HC05C4A Timer Rev. 4.0 — MOTOROLA ...
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General Release Specification — MC68HC05C4A Section 9. Serial Communications Interface (SCI) 9.1 Contents 9.2 9.3 9.4 9.5 9.5.1 9.5.1.1 9.5.1.2 9.5.1.3 9.5.1.4 9.5.1.5 9.5.2 9.5.2.1 9.5.2.2 9.5.2.3 9.5.2.4 9.5.2.5 9.5.2.6 9.6 9.6.1 9.6.2 9.6.3 9.6.4 9.6.5 9.2 Introduction The serial ...
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Serial Communications Interface (SCI) 9.3 Features Features of the SCI module include: • • • • • • • • • 9.4 SCI Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in START START General Release ...
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SCI Operation The SCI allows full-duplex, asynchronous, RS232 or RS422 serial communication between the MCU and remote devices, including other MCUs. The SCI’s transmitter and receiver operate independently, although they use the same baud-rate generator. The following paragraphs describe ...
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Serial Communications Interface (SCI) When the shift register is not transmitting a character, the PD1/TDO pin goes to the idle condition, logic 1. If software clears the TE bit during the idle condition, and while TDRE is set, the transmitter ...
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Break Characters Writing a logic 1 to the SBK bit in SCCR2 loads the shift register with a break character. A break character contains all logic 0s and has no start and stop bits. Break character length depends on ...
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Serial Communications Interface (SCI) 9.5.2 Receiver Figure 9-3 PD0/ PIN BUFFER RDI AND CONTROL SCI INTERRUPT REQUEST BAUD RATE REGISTER (BAUD) SCI CONTROL REGISTER 1 (SCCR1) SCI CONTROL REGISTER 2 (SCCR2) SCI STATUS REGISTER (SCSR) SCI DATA REGISTER (SCDR) General ...
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Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCCR1) determines character length. When receiving 9-bit data, bit R8 in SCCR1 is the ninth bit (bit ...
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Serial Communications Interface (SCI) 9.5.2.4 Receiver Noise Immunity The data recovery logic samples each bit 16 times to identify and verify the start bit and to detect noise. Any conflict between noise-detection samples sets the noise flag (NF) in the ...
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SCI I/O Registers These I/O registers control and monitor SCI operation: • • • • 9.6.1 SCI Data Register The SCI data register is the buffer for characters received and for characters transmitted. Address: Reset: MC68HC05C4A Rev. 4.0 — ...
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Serial Communications Interface (SCI) 9.6.2 SCI Control Register 1 SCI control register 1 has these functions: • • • Address: Read: Write: Reset: R8 — Bit 8 (Received) When the SCI is receiving 9-bit characters the ninth bit ...
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M — Character Length This read/write bit determines whether SCI characters are 8 bits long or 9 bits long. The ninth bit can be used as an extra stop bit receiver wakeup signal mark or ...
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Serial Communications Interface (SCI) 9.6.3 SCI Control Register 2 SCI control register 2 has these functions: • • • • • • Address: Read: Write: Reset: TIE — Transmit Interrupt Enable This read/write bit enables SCI interrupt requests when the ...
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ILIE — Idle Line Interrupt Enable This read/write bit enables SCI interrupt requests when the IDLE bit becomes set. Reset clears the ILIE bit. TE — Transmit Enable Setting this read/write bit begins the transmission by sending a preamble of ...
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Serial Communications Interface (SCI) 9.6.4 SCI Status Register The SCI status register contains flags to signal the following conditions: • • • • • • • Address: Read: Write: Reset: TDRE — Transmit Data Register Empty This clearable, read-only bit ...
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SCSR with TC set, and then writing to the SCDR. Reset sets the TC bit. Software must initialize the TC bit to logic 0 to avoid an instant interrupt request when turning on the transmitter. RDRF ...
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Serial Communications Interface (SCI) NF — Receiver Noise Flag This clearable, read-only bit is set when noise is detected in data received in the SCI data register. Clear the NF bit by reading the SCSR and then reading the SCDR. ...
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SCR2–SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate, as shown in Table Table 9-3 frequencies of 2 MHz, 4 MHz, and 4.194304 MHz. MC68HC05C4A Rev. 4.0 — MOTOROLA Table 9-1. Baud Rate Generator ...
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Serial Communications Interface (SCI) Table 9-3. Baud Rate Selection Examples – –SCR SCP1 SCP0 SCR2 00 000 00 001 00 010 00 011 00 100 00 101 00 110 00 111 01 000 01 001 01 010 01 011 01 ...
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General Release Specification — MC68HC05C4A Section 10. Serial Peripheral Interface (SPI) 10.1 Contents 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.5 10.6 10.6.1 10.6.2 10.6.3 10.2 Introduction The serial peripheral interface (SPI interface built into the MC68HC05 MCU ...
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Serial Peripheral Interface (SPI) 10.3 Features • • • • • • • • • 10.4 SPI Signal Description The four basic signals (MOSI, MISO, SCK, and SS) are described in the following paragraphs. Each signal function is described for ...
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Serial Clock (SCK) The master clock is used to synchronize data movement both in and out of the device through its MOSI and MISO lines. The master and slave devices are capable of exchanging a byte of information during ...
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Serial Peripheral Interface (SPI) 10.4.4 Slave Select (SS) The slave select (SS) input line is used to select a slave device. It has to be low prior to data transactions and must stay low for the duration of the transaction. ...
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INTERNAL MCU CLOCK DIVIDER SPI CLOCK (MASTER) SELECT SPI CONTROL SPI STATUS REGISTER SPI INTERRUPT Figure 10-2. Serial Peripheral Interface Block Diagram MC68HC05C4A Rev. 4.0 — MOTOROLA MSB LSB 8-BIT SHIFT REG READ DATA BUFF CLOCK ...
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Serial Peripheral Interface (SPI slave mode, the slave select start logic receives a logic low at the SS pin and a clock at the SCK pin. Thus, the slave is synchronized with the master. Data from the master ...
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Serial Peripheral Control Register Address: Read: Write: Reset: SPIE — Serial Peripheral Interrupt Enable SPE — Serial Peripheral System Enable MSTR — Master Mode Select CPOL — Clock Polarity When the clock polarity bit is cleared and data is ...
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Serial Peripheral Interface (SPI) As soon as SS goes low, the transaction begins and the first edge on SCK invokes the first data sample. When CPHA = 1, the SS pin may be thought simple output enable ...
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WCOL — Write Collision The write collision bit is set when an attempt is made to write to the serial peripheral data register while data transfer is taking place. If CPHA transfer is said to begin when ...
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Serial Peripheral Interface (SPI) 10.6.3 Serial Peripheral Data I/O Register The serial peripheral data I/O register is used to transmit and receive data on the serial bus. Only a write to this register will initiate transmission/reception of another byte, and ...
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General Release Specification — MC68HC05C4A 11.1 Contents 11.2 11.3 11.4 11.4.1 11.4.2 11.2 Introduction The MCU has two modes of operation: user mode and self-check mode. Table 11-1 where V 11.3 User Mode In user mode, the address and data ...
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Operating Modes 11.4 Self-Check Mode Self-check mode is entered upon the rising edge of RESET if the IRQ pin 11.4.1 Self-Check Tests The self-check ROM at mask ROM location $1F00–$1FEF determines if the MCU is functioning properly. ...
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ROM — Exclusive OR with odd ones parity result 6. SPI — Transmission test checks for SPIF and WCOL flags The self-check circuit is shown in 11.4.2 Self-Check Results Table 11-2 Perform these three steps to activate the self-check ...
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Operating Modes MC34064 4.7 k NOTES 5 TCMP = NC Figure 11-2. Self-Check Circuit Schematic General Release Specification MC68H05C4A RESET IRQ ...
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General Release Specification — MC68HC05C4A 12.1 Contents 12.2 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.5 12.6 MC68HC05C4A Rev. 4.0 — MOTOROLA Section 12. Instruction Set Introduction ...............................................................................96 Addressing Modes ....................................................................96 Inherent ...
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Instruction Set 12.2 Introduction The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication ...
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Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator ...
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Instruction Set 12.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the ...
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Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch ...
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Instruction Set 12.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. General ...
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Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. MC68HC05C4A Rev. ...
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Instruction Set 12.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt ...
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MC68HC05C4A Rev. 4.0 — MOTOROLA Table 12-3. Jump and Branch Instructions Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if ...
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Instruction Set 12.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the ...
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Control Instructions These instructions act on CPU registers and control CPU operation during program execution. MC68HC05C4A Rev. 4.0 — MOTOROLA Table 12-5. Control Instructions Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt ...
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Instruction Set 12.5 Instruction Set Summary Table 12-6. Instruction Set Summary Source Operation Form ADC # opr ADC opr ADC opr Add with Carry ADC opr ,X ADC opr ,X ADC ,X ADD # opr ADD opr ADD opr Add ...
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Table 12-6. Instruction Set Summary (Continued) Source Operation Form BHI rel Branch if Higher BHS rel Branch if Higher or Same BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT # opr BIT opr ...
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Instruction Set Table 12-6. Instruction Set Summary (Continued) Source Operation Form BSR rel Branch to Subroutine CLC Clear Carry Bit CLI Clear Interrupt Mask CLR opr CLRA CLRX Clear Byte CLR opr ,X CLR ,X CMP # opr CMP opr ...
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Table 12-6. Instruction Set Summary (Continued) Source Operation Form JMP opr JMP opr JMP opr ,X Unconditional Jump JMP opr ,X JMP ,X JSR opr JSR opr JSR opr ,X Jump to Subroutine JSR opr ,X JSR ,X LDA # ...
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Instruction Set Table 12-6. Instruction Set Summary (Continued) Source Operation Form ROL opr ROLA ROLX Rotate Byte Left through Carry Bit ROL opr ,X ROL ,X ROR opr RORA RORX Rotate Byte Right through Carry Bit ROR opr ,X ROR ...
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Table 12-6. Instruction Set Summary (Continued) Source Operation Form SWI Software Interrupt TAX Transfer Accumulator to Index Register TST opr TSTA TSTX Test Memory Byte for Negative or Zero TST opr ,X TST ,X TXA Transfer Index Register to Accumulator ...
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Bit Manipulation Branch DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR ...
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General Release Specification — MC68HC05C4A 13.1 Contents 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 3.3 V Control Timing ...............................................................123 13.11 5.0 V Serial Peripheral Interface Timing .................................126 13.12 3.3 V Serial Peripheral Interface Timing .................................127 13.2 Introduction This ...
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Electrical Specifications 13.3 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply ...
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Operating Temperature Range Operating Temperature Range MC68HC05C4AP, FN MC68HC05C4ACP, CFN, CB, CFB NOTES Plastic dual in-line package (PDIP Plastic-leaded chip carrier (PLCC Extended temperature range (– ...
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Electrical Specifications 13.6 Power Considerations The average chip-junction temperature, T Where For most applications, P Following is an approximate relationship between P neglecting P Solving equations (1) and (2) for K gives: where K is ...
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TEST POINT C SEE TABLE MC68HC05C4A Rev. 4.0 — MOTOROLA Pins PA7–PA0 R2 SEE TABLE PB7–PB0 PC7–PC0 PD5–PD0, PD7 R1 SEE TABLE Pins PA7–PA0 PB7–PB0 PC7–PC0 PD5–PD0, PD7 ...
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Electrical Specifications 13.7 5 Electrical Characteristics Characteristic (Note 2) Output Voltage I = 10.0 A Load I = –10.0 A Load Output High Voltage (I = –0.8 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP Load (I = –1.6 mA) PD4–PD1 ...
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V DC Electrical Characteristics Characteristic (Note 2) Output Voltage I = 10.0 A Load I = –10.0 A Load Output High Voltage (I = –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP Load (I = –0.4 mA) PD4–PD1 Load (I ...
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Electrical Specifications 5.00 mA 4.00 mA 3.00 mA 2.00 mA 1.00 mA General Release Specification 120 – 85C 0.5 MHz 1.0 MHz INTERNAL CLOCK FREQUENCY (XTAL 2) Figure 13-2. Maximum Supply ...
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MC68HC05C4A Rev. 4.0 — MOTOROLA 1. 3 – 1.00 mA 500 mA 0.5 MHz INTERNAL CLOCK FREQUENCY (XTAL 2) Figure 13-3. Maximum Supply Current Versus Internal Clock Frequency, V ...
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Electrical Specifications 13.9 5.0 V Control Timing Characteristic Oscillator Frequency Crystal External Clock Cycle Time Crystal External Clock Internal Clock Cycle Time Crystal Oscillator Startup Time Stop Recovery Startup Time (Crystal Oscillator) RESET Pulse Width Timer Resolution (Note 2) Input ...
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V Control Timing Characteristic Oscillator Frequency Crystal External Clock Internal Operating Frequency Crystal External Clock Internal Clock Cycle Time Crystal Oscillator Startup Time Stop Recovery Startup Time (Crystal Oscillator) RESET Pulse Width Timer Resolution (Note 2) Input Capture ...
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Electrical Specifications IRQ PIN a. Edge-Sensitive Trigger Condition. The minimum pulse width (t or 250 MHz). The period t OP execute the interrupt service routine plus 19 t IRQ NORMALLY . USED WITH ...
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OSC t RL RESET t ILIH 2 IRQ 3 IRQ INTERNAL CLOCK INTERNAL ADDRESS BUS NOTES: 1. Represents the internal clocking of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level- and edge-sensitive mask option ...
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Electrical Specifications 13.11 5.0 V Serial Peripheral Interface Timing Num Characteristic Operating Frequency Master Slave Cycle Time 1 Master Slave Enable Lead Time 2 Master Slave Enable Lag Time 3 Master Slave Clock (SCK) High Time 4 Master Slave Clock ...
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V Serial Peripheral Interface Timing Num Characteristic Operating Frequency Master Slave Cycle Time 1 Master Slave Enable Lead Time 2 Master Slave Enable Lag Time 3 Master Slave Clock (SCK) High Time 4 Master Slave Clock (SCK) Low ...
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Electrical Specifications SS SS PIN OF MASTER HELD HIGH (INPUT) SCK (CPOL = 0) NOTE (OUTPUT) SCK (CPOL = 1) NOTE (OUTPUT) MISO (INPUT) 10 (ref) MOSI (OUTPUT) 13 NOTE: This first clock edge is generated internally, but is not ...
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SS (INPUT) SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO SLAVE (INPUT) 6 MOSI MSB IN (OUTPUT) NOTE: Not defined, but normally MSB of character just received. SS (INPUT) SCK (CPOL = 0) (INPUT) 2 ...
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Electrical Specifications General Release Specification 130 Electrical Specifications MC68HC05C4A Rev. 4.0 — MOTOROLA ...
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General Release Specification — MC68HC05C4A 14.1 Contents 14.2 14.3 14.4 14.5 14.6 14.2 Introduction This section describes the dimensions of the dual in-line package (DIP), plastic shrink dual in-line package (SDIP), plastic leaded chip carrier (PLCC), and quad flat pack ...
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Mechanical Specifications 14.3 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03 14.4 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01 General Release Specification 132 21 ...
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Plastic Leaded Chip Carrier (PLCC) (Case 777-02) -N- - 0.010 (0.25) T L-M NOTES: 1. DATUMS -L-, -M-, AND -N- ARE DETERMINED WHERE TOP OF LEAD SHOLDERS EXITS ...
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Mechanical Specifications 14.6 44-Lead Quad Flat Pack (QFP) (Case 824A- -H- W DETAIL C General Release Specification 134 -B- B DETAIL ...
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General Release Specification — MC68HC05C4A 15.1 Contents 15.2 15.3 15.4 15.5 15.6 15.7 15.2 Introduction This section contains instructions for ordering custom-masked ROM MCUs. 15.3 MCU Ordering Forms To initiate an order for a ROM-based MCU, first obtain the current ...
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Ordering Information The current MCU ordering form is also available through the Motorola Freeware Bulletin Board Service (BBS). The telephone number is (512) 891-FREE. After making the connection, type bbs in lowercase letters. Then press the return key to start ...
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NOTE: Begin the application program at the first user ROM location. Program addresses must correspond exactly to the available on-chip user ROM addresses as shown in the memory map. Write $00 in all non-user ROM locations or leave all non-user ...
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Ordering Information Check the listing verify file thoroughly, then complete and sign the listing verify form and return the it to Motorola. The signed listing verify form constitutes the contractual agreement for the creation of the custom mask. 15.6 ROM ...
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MC Order Numbers Table 15-1 types. 40-Pin Plastic Dual In-Line Package (DIP) 42-Pin Plastic Shrink Dual In-Line Package (SDIP) 44-Lead Plastic Leaded Chip Carrier (PLCC) 44-Lead Quad Flat Pack (QFP) 40-Pin Plastic Dual In-Line Package (DIP) 42-Pin Plastic Shrink ...
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Ordering Information General Release Specification 140 Ordering Information MC68HC05C4A Rev. 4.0 — MOTOROLA ...
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General Release Specification — MC68HC05C4A A.1 Contents A.2 A.3 A.4 A.5 A.6 A.2 Introduction Appendix A introduces the MC68HCL05C4A, a low-power version of the MC68HC05C4A. The technical data applying to the MC68HC05C4A applies to the MC68HCL05C4A with the exceptions given ...
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MC68HCL05C4A A.4 2.5–3 Electrical Characteristics Characteristic Output High Voltage (I = –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP Load (I = –0.4 mA) PD4–PD1 Load (I = –1.5 mA) PC7 Load Output Low Voltage (I = 0.4 mA) PA7–PA0, ...
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A.6 Low-Power Supply Current Characteristic (Note 1) Supply Current (4.5–5.5 Vdc @ f Run Wait Stop +70 C (Standard) Supply Current (2.4–3.6 Vdc @ f Run (Note 2) Wait (Note 3) Stop (Note 4) 25 ...
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MC68HCL05C4A General Release Specification 144 MC68HCL05C4A MC68HC05C4A Rev. 4.0 — MOTOROLA ...
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General Release Specification — MC68HC05C4A B.1 Contents B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.2 Introduction Appendix B introduces the MC68HSC05C4A, a high-speed version of the MC68HC05C4A. The technical data applying to the MC68HC05C4A applies to the MC68HSC05C4A with the ...
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MC68HSC05C4A B.3 High-Speed Operating Temperature Range The data here replaces the corresponding data in Temperature Operating Temperature Range MC68HSC05C4AP, FN MC68HSC05C4ACP, CFN, CB, CFB NOTES Plastic dual in-line package (PDIP Plastic-leaded chip ...
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B.4 4.5 –5.5 V High-Speed Supply Currents The data in MC68HSC05C4A with the exceptions given in this table. Characteristic (Note 1) Supply Current (4.5–5.5 Vdc @ f Run (Note 2) Wait (Note 3) Stop (Note ...
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MC68HSC05C4A B.5 4.5–5.5 V High-Speed Control Timing The data in with the exceptions in this table. Characteristic Oscillator Frequency Crystal External Clock Internal Operating Frequency (f osc Crystal External Clock Cycle Time Crystal Oscillator Startup Time Stop Recovery Startup Time ...
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B.6 2.4–3.6 V High-Speed Control Timing Characteristic Oscillator Frequency Crystal External Clock Internal Operating Frequency (f Crystal External Clock Cycle Time Crystal Oscillator Startup Time Stop Recovery Startup Time RESET Pulse Width Timer Resolution (Note 1) Input Capture Pulse Width ...
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MC68HSC05C4A B.7 4.5 –5.5 V High-Speed SPI Timing The data in the MC68HSC05C8A with the exceptions given in the following table. Num Characteristic Operating Frequency Master Slave Cycle Time 1 Master Slave Enable Lead Time 2 Master Slave Enable Lag ...
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B.8 2.4–3.6 V High-Speed SPI Timing The data in the MC68HSC05C8A with the exceptions given in the following table. Num Characteristic Operating Frequency Master Slave Cycle Time Master 1 Slave Enable Lead Time Master 2 Slave Enable Lag Time Master ...
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MC68HSC05C4A General Release Specification 152 MC68HSC05C4A MC68HC05C4A Rev. 4.0 — MOTOROLA ...
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General Release Specification — MC68HC05C4A Appendix C. M68HC05Cx Family Feature Comparisons C.1 Contents C.2 C.2 Introduction Refer to M68HC05C Family members. MC68HC05C4A Rev. 4.0 — MOTOROLA Introduction .............................................................................153 Table C-1. M68HC05Cx Feature Comparison .......................154 Table C-1 for a comparison of ...
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C4A 705C4A C8 USER ROM 4160 4160 — 7744 USER EPROM — — 4160 — CODE NO YES YES NO SECURITY RAM 176 176 176 ...
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...