CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 70

• Manufacturer Part Number: CM68HC05C4ACFB
• Description: Microcontroller
• Manufacturer: Motorola / Freescale Semiconductor

Serial Communications Interface (SCI)
9.5.2.4 Receiver Noise Immunity
9.5.2.5 Framing Errors
9.5.2.6 Receiver Interrupts
General Release Specification
70
The data recovery logic samples each bit 16 times to identify and verify
the start bit and to detect noise. Any conflict between noise-detection
samples sets the noise flag (NF) in the SCSR. The NF bit is set at the
same time that the RDRF bit is set.
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error (FE) bit in
the SCSR. The FE bit is set at the same time that the RDRF bit is set.
Three sources can generate SCI receiver interrupt requests:
1. Receive Data Register Full (RDRF) — The RDRF bit in the SCSR
2. Receiver Overrun (OR) — The OR bit in the SCSR indicates that
3. Idle Input (IDLE) — The IDLE bit in the SCSR indicates that 10 or
indicates that the receive shift register has transferred a character
to the SCDR.
the receive shift register shifted in a new character before the
previous character was read from the SCDR.
11 consecutive logic 1s shifted in from the PD0/RDI pin.
Serial Communications Interface (SCI)
MC68HC05C4A
MOTOROLA
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Rev. 4.0