CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 83

• Manufacturer Part Number: CM68HC05C4ACFB
• Description: Microcontroller
• Manufacturer: Motorola / Freescale Semiconductor

10.4.3 Serial Clock (SCK)
MC68HC05C4A
MOTOROLA
—
Rev. 4.0
The master clock is used to synchronize data movement both in and out
of the device through its MOSI and MISO lines. The master and slave
devices are capable of exchanging a byte of information during a
sequence of eight clock cycles. Since SCK is generated by the master
device, this line becomes an input on a slave device.
As shown in
chosen by using control bits CPOL and CPHA in the serial peripheral
control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the
MOSI line one-half cycle before the clock edge (SCK), so the slave
device can latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the
clock rate. In a slave device, SPR0 and SPR1 have no effect on the SPI
operation.
MISO/MOSI
SCK
SCK
SCK
SCK
SS
Serial Peripheral Interface (SPI)
Figure
MSB
Figure 10-1. Data Clock Timing Diagram
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
10-1, four possible timing relationships may be
6
5
4
3
Serial Peripheral Interface (SPI)
General Release Specification
2
SPI Signal Description
1
0
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