CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 60

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CM68HC05C4ACFB

Manufacturer Part Number
CM68HC05C4ACFB
Description
Microcontroller
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
Timer
General Release Specification
60
8.7 Timer Status Register
Address:
The TSR is a read-only register containing three status flag bits.
ICF — Input Capture Flag
OCF — Output Compare Flag
TOF — Timer Overflow Flag
Bits 0–4 — Not used
Accessing the timer status register satisfies the first condition required
to clear status bits. The remaining step is to access the register
corresponding to the status bit.
Reset:
Read:
Write:
Always read 0
1 = Flag set when selected polarity edge is sensed by input capture
0 = Flag cleared when TSR and input capture low register ($15) are
1 = Flag set when output compare register contents match the free-
0 = Flag cleared when TSR and output compare low register ($17)
1 = Flag set when free-running counter transition from $FFFF to
0 = Flag cleared when TSR and counter low register ($19) are
U = Unaffected
Bit 7
$13
ICF
edge detector
accessed
running counter contents
are accessed
$0000 occurs
accessed
U
Figure 8-5. Timer Status Register (TSR)
OCF
U
6
Timer
TOF
U
5
4
0
0
3
0
0
MC68HC05C4A
2
0
0
MOTOROLA
1
0
0
Rev. 4.0
Bit 0
0
0

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