CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 58

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CM68HC05C4ACFB

Manufacturer Part Number
CM68HC05C4ACFB
Description
Microcontroller
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
Timer
General Release Specification
58
8.6 Timer Control Register
Address:
the time used in the input capture software routine and its interaction
with the main program to determine the minimum pulse period.
A read of the input capture register LSB ($15) does not inhibit the free-
running counter transfer, since they occur on opposite edges of the
internal bus clock.
function.
The TCR is a read/write register containing five control bits. Three bits
control interrupts associated with the timer status register flags ICF,
OCF, and TOF.
Reset:
Read:
Write:
TCMP
U = Unaffected
Bit 7
ICIE
$12
SELECT/DETECT
0
LOGIC
EDGE
Figure 8-4. Timer Control Register (TCR)
OCIE
Figure 8-3. Input Capture Operation
6
0
Figure 8-3
Timer
LATCH
TIMER CONTROL REGISTER
TOIE
5
0
15
15
INPUT CAPTURE REGISTER HIGH
$0012
shows the logic of the input capture
TIMER REGISTER HIGH
4
0
0
$0018
$0014
3
0
0
TIMER STATUS REGISTER
MC68HC05C4A
8 7
8 7
INPUT CAPTURE REGISTER LOW
$0013
2
0
0
TIMER REGISTER LOW
IEDG
$0019
$0015
MOTOROLA
1
U
INTERRUPT
REQUEST
Rev. 4.0
TIMER
OLVL
Bit 0
0
0
0

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