CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 88

• Manufacturer Part Number: CM68HC05C4ACFB
• Description: Microcontroller
• Manufacturer: Motorola / Freescale Semiconductor

Serial Peripheral Interface (SPI)
10.6.2 Serial Peripheral Status Register
General Release Specification
88
Address:
SPR1 and SPR0 — SPI Clock Rate Selects
SPIF — SPI Transfer Complete Flag
Reset:
Read:
Write:
As soon as SS goes low, the transaction begins and the first edge on
SCK invokes the first data sample. When CPHA = 1, the SS pin may
be thought of as a simple output enable control. See
These two bits select one of four baud rates to be used as SCK if the
device is a master; however, they have no effect in the slave mode.
See
The serial peripheral data transfer flag bit is set upon completion of
data transfer between the processor and external device. If SPIF
goes high and if SPIE is set, a serial peripheral interrupt is generated.
Clearing the SPIF bit is accomplished by reading the SPSR (with
SPIF set) followed by an access of the SPDR. Unless SPSR is read
(with SPIF set) first, attempts to write to SPDR are inhibited.
Table
$000B
SPIF
Bit 7
0
Serial Peripheral Interface (SPI)
SPR1
Table 10-1. Serial Peripheral Rate Selection
10-1.
Figure 10-5. SPI Status Register (SPSR)
0
0
1
1
= Unimplemented
WCOL
6
0
5
0
0
SPR0
0
1
0
1
MODF
U = Unaffected
4
0
3
0
0
Bus Clock Divided By
MC68HC05C4A
2
0
0
16
32
2
4
Figure
U
1
0
MOTOROLA
—
10-1.
Rev. 4.0
Bit 0
0
0