CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 76

• Manufacturer Part Number: CM68HC05C4ACFB
• Description: Microcontroller
• Manufacturer: Motorola / Freescale Semiconductor

Serial Communications Interface (SCI)
9.6.4 SCI Status Register
General Release Specification
76
The SCI status register contains flags to signal the following conditions:
TDRE — Transmit Data Register Empty
TC — Transmission Complete
Address:
•
•
•
•
•
•
•
This clearable, read-only bit is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set, and then writing to the SCDR.
Reset sets the TDRE bit. Software must initialize the TDRE bit to logic
0 to avoid an instant interrupt request when turning on the transmitter.
This clearable, read-only bit is set when the TDRE bit is set, and no
data, preamble, or break character is being transmitted. TC generates
an interrupt request if the TCIE bit in SCCR2 is also set. Clear the TC
Reset:
Read:
Write:
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing Error
Serial Communications Interface (SCI)
$0010
TDRE
Bit 7
Figure 9-7. SCI Status Register (SCSR)
= Unimplemented
TC
6
RDRF
5
Unaffected by Reset
IDLE
4
OR
3
MC68HC05C4A
NF
2
FE
1
MOTOROLA
—
Rev. 4.0
Bit 0
0