CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 77

• Manufacturer Part Number: CM68HC05C4ACFB
• Description: Microcontroller
• Manufacturer: Motorola / Freescale Semiconductor

MC68HC05C4A
MOTOROLA
—
Rev. 4.0
RDRF — Receive Data Register Full
IDLE — Receiver Idle
OR — Receiver Overrun
bit by reading the SCSR with TC set, and then writing to the SCDR.
Reset sets the TC bit. Software must initialize the TC bit to logic 0 to
avoid an instant interrupt request when turning on the transmitter.
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. RDRF generates an
interrupt request if the RIE bit in SCCR2 is also set. Clear the RDRF
bit by reading the SCSR with RDRF set, and then reading the SCDR.
Reset clears the RDRF bit.
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an interrupt request if
the ILIE bit in SCCR2 is also set. Clear the IDLE bit by reading the
SCSR with IDLE set, and then reading the SCDR. Reset clears the
IDLE bit.
This clearable, read-only bit is set if the SCDR is not read before the
receive shift register receives the next word. OR generates an
interrupt request if the RIE bit in SCCR2 is also set. The data in the
shift register is lost, but the data already in the SCDR is not affected.
Clear the OR bit by reading the SCSR with OR set and then reading
the SCDR. Reset clears the OR bit.
1 = No transmission in progress
0 = Transmission in progress
1 = Received data available in SCDR
0 = Received data not available in SCDR
1 = Receiver input idle
0 = Receiver input not idle
1 = Receiver shift register full and RDRF = 1
0 = No receiver overrun
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
General Release Specification
SCI I/O Registers
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