CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 75

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CM68HC05C4ACFB

Manufacturer Part Number
CM68HC05C4ACFB
Description
Microcontroller
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
MC68HC05C4A
MOTOROLA
Rev. 4.0
ILIE — Idle Line Interrupt Enable
TE — Transmit Enable
RE — Receive Enable
RWU — Receiver Wakeup Enable
SBK — Send Break
This read/write bit enables SCI interrupt requests when the IDLE bit
becomes set. Reset clears the ILIE bit.
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PD1/TDO pin. Reset clears the TE bit.
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver and receiver interrupts but does not affect the
receiver interrupt flags. Reset clears the RE bit.
This read/write bit puts the receiver in a standby state. Typically, data
transmitted to the receiver clears the RWU bit and returns the receiver
to normal operation. The WAKE bit in SCCR1 determines whether an
idle input or an address mark brings the receiver out of the standby
state. Reset clears the RWU bit.
Setting this read/write bit continuously transmits break codes in the
form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops
the break codes and transmits a logic 1 as a start bit. Reset clears the
SBK bit.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
1 = Transmission enabled
0 = Transmission disabled
1 = Receiver enabled
0 = Receiver disabled
1 = Standby state
0 = Normal operation
1 = Break codes being transmitted
0 = No break codes being transmitted
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
General Release Specification
SCI I/O Registers
75

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