CM68HC05C4ACFB Motorola / Freescale Semiconductor, CM68HC05C4ACFB Datasheet - Page 124

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CM68HC05C4ACFB

Manufacturer Part Number
CM68HC05C4ACFB
Description
Microcontroller
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
Electrical Specifications
General Release Specification
124
NORMALLY
USED WITH
WIRED-OR
ADDRESS BUS
NOTES:
DATA BUS
INTERNAL
INTERNAL
INTERNAL
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
1. Internal clock, internal address bus, and internal data bus are not available externally.
CLOCK
RESET
IRQ PIN
1
1
1
2
INTERNAL
a. Edge-Sensitive Trigger Condition. The minimum pulse width (t
IRQ
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low, the next interrupt
IRQ
.
.
.
IRQ
or 250 ns (f
execute the interrupt service routine plus 19 t
1
n
is recognized.
OP
Figure 13-5. External Interrupt Timing
= 1 MHz). The period t
Figure 13-6. External Reset Timing
1FFE
t
RL
t
ILIH
Electrical Specifications
1FFE
t
ILIL
ILIH
should not be less than the number of t
t
ILIL
1FFE
cyc
cycles.
1FFE
NEW
PCH
ILIH
1FFF
) is either 125 ns (f
NEW
PCL
NEW PC
cyc
CODE
MC68HC05C4A
OP
cycles it takes to
OP
= 2.1 MHz)
MOTOROLA
Rev. 4.0

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