MBM29QM12DH Fujitsu Microelectronics, Inc., MBM29QM12DH Datasheet - Page 11

• Manufacturer Part Number: MBM29QM12DH
• Description: Page Mode Flash Memory 128m 8m X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

10
MBM29QM12DH
(Continued)
Legend:
RA
PA
SA
BA
RD
PD
SGA
WPH
SD
HRA
HRBA
RD (0)
RD (1)
OPBP
PWA/PWD
PL
SPML
WP
Password
Mode Locking
Bit Program
Persistent
Protection
Mode Locking
Bit Program
PPB Program
PPB Verify
All PPB Erase
PPB Lock Bit
Set
PPB Lock Bit
Verify
DPB Write
DPB Erase
DPB Verify
Command
Sequence
Address of the sector to be erased. The combination of A
Address of the memory location to be read
Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
A
Bank Address. Address setted by A
Data read from location RA during read operation.
Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
Sector group address to be protected.
Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
Address of the HiddenROM area Word Mode : 000000h to 00007Fh
Bank Address of the HiddenROM area (A
Read Data bit. If programmed, DQ
Read Data bit. If programmed, DQ
Password Address/Password Data
(A
(A
(A
(A
(A
12
7
7
7
7
7
will uniquely select any sector.
, A
, A
, A
, A
, A
Write
Req’
Bus
cles
Cy-
6
6
6
6
6
d
6
6
6
4
4
3
4
4
4
4
, A
, A
, A
, A
, A
5
5
5
5
5
, A
, A
, A
, A
, A
Addr. Data Addr. Data Addr. Data
555h AAh 2AAh 55h 555h 60h
555h AAh 2AAh 55h 555h 60h SPML 68h SPML 48h
555h AAh 2AAh 55h 555h 60h
555h AAh 2AAh 55h
555h AAh 2AAh 55h 555h 60h
555h AAh 2AAh 55h 555h 78h
555h AAh 2AAh 55h
555h AAh 2AAh 55h 555h 48h
555h AAh 2AAh 55h 555h 48h
555h AAh 2AAh 55h
First Bus
4
4
4
4
4
Cycle
Write
, A
, A
, A
, A
, A
3
3
3
3
3
, A
, A
, A
, A
, A
2
2
2
2
2
, A
, A
, A
, A
, A
-60
1
1
1
1
1
, A
, A
, A
, A
, A
Second
Cycle
Write
0
0
0
0
0
Bus
) is (0, 0, 0, 0, 0, 0, 1, 0)
) is (0, 0, 0, 1, 1, 0, 1, 0)
) is (0, 0, 0, 0, 1, 0, 1, 0)
) is (0, 0, 0, 1, 0, 0, 1, 0)
) is (0, 0, 0, 0, 0, 0, 1, 0)
0
1
22
, A
555h
555h
555h
Third Bus
(BA)
(BA)
(BA)
1, if erase, DQ
1, if erase, DQ
Cycle
21
Write
, A
22
20
90h
58h
58h
A
will select Bank A, Bank B, Bank C and Bank D.
21
Fourth Bus
SGA
SGA
Read/Write
Addr.
A
WP
WP
WP
SA
SA
SA
SA
PL
—
0
1
20
Cycle
0
0
22
V
, A
IL
Data
68h
X1h
X0h
68h
60h
RD
RD
RD
(0)
(1)
(0)
)
—
21
, A
20
Write Cycle
SGA
SGA
Addr. Data Addr. Data Addr. Data
, A
Fifth Bus
WP
WP
PL
—
—
—
—
—
—
19
, A
18
48h
48h
40h
—
—
—
—
—
—
, A
17
, A
XXXh
XXXh
XXXh
XXXh
Sixth Bus
—
—
—
—
—
—
16
Cycle
Write
, A
15
RD
RD
RD
RD
(0)
(0)
(0)
(0)
—
—
—
—
—
—
, A
14
, A
Seventh
—
—
—
—
—
—
—
—
—
—
13
Cycle
Write
Bus
and
—
—
—
—
—
—
—
—
—
—