MBM29QM12DH Fujitsu Microelectronics, Inc., MBM29QM12DH Datasheet - Page 44

• Manufacturer Part Number: MBM29QM12DH
• Description: Page Mode Flash Memory 128m 8m X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

Low V
Write Pulse “Glitch” Protection
Logical Inhibit
Power-Up Write Inhibit
To avoid initiation of a write cycle during V
than V
disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
If the Embedded Erase Algorithm is interrupted, the intervened erasing sector (s) is (are) not valid.
Noise pulses of less than 3 ns (typical) on OE, CE or WE will not initiate a write cycle.
Writing is inhibited by holding any one of OE
must be a logical zero while OE is a logical one.
Power-up of the device with WE
The internal state machine is automatically reset to the read mode on power-up.
CC
CC
Write Inhibit
LKO
level is greater than V
(Min) . If V
CC
V
LKO
LKO
, the command register is disabled and all internal program/erase circuits are
. It is the user’s responsibility to ensure that the control pins are logically correct
CE
CC
V
is above V
CC
IL
and OE
power-up and power-down, a write cycle is locked out for V
V
IL
, CE
LKO
V
(Min) .
IH
V
will not accept commands on the rising edge of WE.
IH
or WE
MBM29QM12DH
V
IH
. To initiate a write cycle CE and WE
CC
less
-60
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