MBM29QM12DH Fujitsu Microelectronics, Inc., MBM29QM12DH Datasheet - Page 43

• Manufacturer Part Number: MBM29QM12DH
• Description: Page Mode Flash Memory 128m 8m X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

42
MBM29QM12DH
Reading Toggle Bits 3DQ
* : Successive reads from the erasing or erase-suspend sector will cause DQ
RY/BY
Ready/Busy
Data Protection
Program
Erase
Erase-Suspend Read
Erase-Suspend Program
(Erase-Suspended Sector)
Whenever the system initially begins reading toggle bit status, it must read DQ
to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ
However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
gone high. The system may continue to monitor the toggle bit and DQ
mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the
status of the operation. (Refer to “Toggle Bit Algorithm” in “ FLOW CHART”.)
erase suspend sector address will indicate logic “1” at the DQ
The device provides a RY/BY open-drain output pin as a way to indicate to the host system that Embedded
Algorithms are either in progress or have been completed. If output is low, the device is busy with either a program
or erase operation. If output is high, the device is ready to accept any read/write or erase operation. If the device
is placed in an Erase Suspend mode, RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during RESET pulse. Refer to “RY/BY Timing Diagram during Program/Erase Operation Timing
Diagram” in “ TIMING DIAGRAM” and “RESET, RY/BY Timing Diagram” in “ TIMING DIAGRAM” for a detailed
timing diagram. The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transitions. During power-up, the device automatically resets the internal
state machine in Read mode. Also, with its control register architecture, alteration of memory contents only
occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from V
and power-down transitions or system noise.
Mode
7
6
to DQ
/DQ
2
0
on the following read cycle.
-60
Toggle Bit Status Table
5
DQ
DQ
DQ
is high (see the section on DQ
0
1
7
7
7
2
bit.
Toggle
Toggle
Toggle
DQ
5
1
through successive read cycles, deter-
6
2
5
to toggle. Reading from the non
) . If it is, the system should then
7
to DQ
0
at least twice in a row
Toggle*
Toggle
DQ
1*
1
CC
2
power-up
5
has not
CC
.
5