MBM29QM12DH Fujitsu Microelectronics, Inc., MBM29QM12DH Datasheet - Page 42

• Manufacturer Part Number: MBM29QM12DH
• Description: Page Mode Flash Memory 128m 8m X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

DQ
Exceeded Timing Limits
DQ
Sector Erase Timer
DQ
Toggle Bit II
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “
Toggle Bit I timing specifications and diagrams.
DQ
these conditions DQ
not successfully completed. Data Polling is only operating function of the device under this condition. The CE
circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins
will control the output disable functions as described in “MBM29QM12DH User Bus Operations Table” in “
DEVICE BUS OPERATION”.
The DQ
this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads valid data on DQ
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.
If this occurs, reset device with the command sequence.
After completion of the initial sector erase command sequence, sector erase time-out begins. DQ
low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command
sequence.
If Data Polling or the Toggle Bit I indicates that a valid erase command has been written, DQ
determine whether the sector erase timer window is still open. If DQ
cycle has begun. If DQ
command has been accepted, the system software should check the status of DQ
subsequent Sector Erase command. If DQ
been accepted.
See “Hardware Sequence Flags Table” in “ COMMAND DEFINITION” : Hardware Sequence Flags.
This toggle bit II, along with DQ
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
suspended sector will indicate a logic “1” at the DQ
DQ
Program operation is in progress. The behavior of these two status bits, along with that of DQ
as follows :
For example, DQ
(DQ
vs. DQ
Furthermore DQ
if this bit is read from an erasing sector.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
5
3
2
5
2
6
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase
will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under
is different from DQ
toggles while DQ
6
” in “ TIMING DIAGRAM”.
5
failure condition may also appear if a user tries to program a non-blank location without pre-erase. In
2
2
can also be used to determine which sector is being erased. At the erase mode, DQ
and DQ
5
will produce “1”. This is a failure condition indicating that the program or erase cycle was
6
7
3
does not.) See also “Toggle Bit Status Table” in “ COMMAND DEFINITION” and “DQ
bit and DQ
is low (“0”) , the device will accept additional sector erase commands. To insure the
2
6
in that DQ
can be used together to determine if the erase-suspend-read mode is in progress.
6
, can be used to determine whether the device is in the Embedded Erase
6
never stop toggling. Once the device has exceeded timing limits, the DQ
6
toggles only when the standard program or Erase, or Erase Suspend
3
were high on the second status check, the command may not have
2
bit.
2
to toggle during the Embedded Erase Algorithm. If the
3
is high (“1”) the internally controlled erase
MBM29QM12DH
3
TIMING DIAGRAM” for the
prior to and following each
3
7
, is summarized
may be used to
3
will remain
2
toggles
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5
2
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