MBM29QM12DH Fujitsu Microelectronics, Inc., MBM29QM12DH Datasheet - Page 40

• Manufacturer Part Number: MBM29QM12DH
• Description: Page Mode Flash Memory 128m 8m X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

All PPB Erase Command
Write Operation Status
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ
*2 : Reading from non-erase suspend sector address will indicate logic “1” at the DQ
In Progress
Exceeded
Time Limits
The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a
specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase
command is written (60h), all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase
command will not execute and the command will time-out without erasing the PPBs. After issuing "WP/60h" at
4th bus cycle, the device requires approximately 1.5 ms time out period for programming the PPB. Then by
writing "SGA WP/40h" at 5th bus cycle, the device outputs verify data at DQ
erased. If not, then the user needs to repeat this program sequence from the 4th cycle of "WP/60h".
It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user
attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time.
Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond
100 cycles is not guaranteed. Writing the HiddenROM Exit Command returns the device back to normal operation.
Detailed in “Hardware Sequence Flags Table” in “ COMMAND DEFINITION” are all the status flags which can
determine the status of the bank for the current mode operation. The read operation from the bank which doesn’t
operate Embedded Algorithm returns data of memory cells. These bits offer a method for determining whether
an Embedded Algorithm is properly completed. The information on DQ
if an address from an erasing sector is consecutively read, the DQ
if an address from a non-erasing sector is consecutively read. This allows users to determine which sectors are
in erase and which are not.
The status flag is not output from banks (non-busy banks) which do not execute Embedded Algorithms. For
example, a bank (busy bank) is executing an Embedded Algorithm. When the read sequence is [1] busy bank
>, [2]
memory cells are output. In the erase-suspend read mode with the same read sequence, DQ
in [1] and [3].
In the erase suspend read mode, DQ
non-busy bank >, [3]
Embedded Program Algorithm
Embedded Erase Algorithm
Program
Suspended Mode
Erase
Suspended Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Suspended Mode
Status
Program Suspend Read
Program Suspend Read
Erase Suspend Read
Erase Suspend Read
Erase Suspend Program
Erase Suspend Program
busy bank >, the DQ
(Non-Program Suspended Sector)
(Program Suspended Sector)
(Erase Suspended Sector)
(Non-Erase Suspended Sector)
(Non-Erase Suspended Sector)
(Non-Erase Suspended Sector)
Hardware Sequence Flags Table
2
is toggled in [1] and [3]. In case of [2], the data of memory cell is output.
6
toggles in the case of [1] and [3]. In case of [2], the data of
2
Data
Data
Data
bit will toggle. However, DQ
DQ
DQ
DQ
DQ
DQ
0
1
0
MBM29QM12DH
7
7
7
7
7
2
is address-sensitive. This means that
0
2
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
. If DQ
Data
Data
Data
to toggle.
DQ
1
6
2
0
bit.
0 then PPB is successfully
Data
Data
Data
DQ
0
0
0
0
1
1
1
5
6
will not be toggled
Data
Data
Data
DQ
2
0
1
0
0
0
1
0
will not toggle
3
Toggle*
Toggle
Data
Data
Data
DQ
N/A
N/A
1*
1
1
2
2
-60
1
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