MBM29QM12DH Fujitsu Microelectronics, Inc., MBM29QM12DH Datasheet - Page 35

• Manufacturer Part Number: MBM29QM12DH
• Description: Page Mode Flash Memory 128m 8m X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

34
MBM29QM12DH
Chip Erase Command
Sector Erase Command
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence, the device will automatically program and verify the entire memory for an all-
zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ
RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command
sequence, and terminates when the data on DQ
device returns to the read mode.
Chip Erase Time; Sector Erase Time
“Embedded Erase
command strings and bus operations.
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE, whichever
happens later, while the command (Data
first. After time-out of “t
begins.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29QM12DH Com-
mand Definitions Table” in “
Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must
be less than “t
that processor interrupts be disabled during this time to guarantee such a condition. The interrupts can reoccur
after the last Sector Erase command is written. A time-out of “t
whichever happens first, will initiate the execution of the Sector Erase command (s) . If another falling edge of
CE or WE, whichever happens first occurs within the “t
determine if the sector erase timer window is still open, see section DQ
device once execution has begun will corrupt the data in the sector. In that case, restart the erase on those
sectors and allow them to complete (refer to Write Operation Status section for Sector Erase Timer operation).
Loading the sector erase buffer may be done in any sequence and with any number of sectors.
Sector erase does not require the user to program the device before erase. The device automatically programs
all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing
a sector, the rest remain unaffected. The system is not required to provide any controls or timings during these
operations.
The system can determine the status of the erase operation by using DQ
RY/BY.
The sector erase begins after the “t
the last sector erase command pulse and terminates when the data on DQ
section), at which time the device returns to the read mode. Data polling and Toggle Bit must be performed at
an address within any of the sectors being erased.
Multiple Sector Erase Time
Sector Erase
In case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which
sectors being erased belong cannot be performed.
“Embedded Erase
command strings and bus operations.
TOW
”. Otherwise, that command will not be accepted and erasure will not start. It is recommended
TM
TM
Algorithm” in “ FLOW CHART” illustrates the Embedded Erase
Algorithm” in “ FLOW CHART” illustrates the Embedded Erase
TOW
” from the rising edge of the last sector erase command, the sector erase operation
DEVICE BUS OPERATION”. This sequence is followed by writes of the Sector
[Sector Erase Time
-60
TOW
” time-out from the rising edge of CE or WE, whichever happens first, for
All sectors
30h) is latched on the rising edge of CE or WE, whichever happens
7
is “1” (see Write Operation Status section), at which time the
Chip Program Time (Preprogramming)
Sector Program Time (Preprogramming) ]
TOW
” time-out window, the timer is reset (monitor DQ
TOW
” from the rising edge of last CE or WE,
3
, Sector Erase Timer). Resetting the
7
7
7
(Data Polling) , DQ
(Data Polling) , DQ
is “1” (see Write Operation Status
TM
TM
Algorithm using typical
Algorithm using typical
6
6
(Toggle Bit) or
(Toggle Bit) or
Number of
3
to