MBM29QM12DH Fujitsu Microelectronics, Inc., MBM29QM12DH Datasheet - Page 26

• Manufacturer Part Number: MBM29QM12DH
• Description: Page Mode Flash Memory 128m 8m X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

Note : Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank
Read Mode
Page Mode Read
Standby Mode
The device has two control functions which are required in order to obtain data at the outputs. CE is the power
control and should be used for a device selection. OE is the output control and should be used to gate data to
the output pins.
Address access time (t
time (t
access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses
have been stable for at least t
up, it is necessary to input hardware reset or to change CE pin from “H” or “L”
The device is capable of fast page mode read. This mode provides faster read access speed by sequential
access within a page. The Page size of the device is 8 words, within the appropriate Page being selected by the
higher address bits A
an asynchronous operation with the microprocessor supplying the specific word location.
The random or initial page access is equal to t
specified by the microprocessor fall within that Page) is equivalent to t
and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast
page mode accesses are obtained by keeping A
There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and
the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET input held at V
this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, V
current (I
these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V
the device requires t
During standby mode, the output is in the high impedance state, regardless of OE input.
“H” or “L”) . Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is set high,
consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) means to specify each of the
Banks.
Case
CE
1
2
3
4
5
6
7
) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable
CC2
) is required even if CE
RH
22
ACC
as a wake-up time for output to be valid for read access.
to A
) is equal to delay from stable addresses to valid output data. The chip enable access
3
and the LSB bits A
ACC
Autoselect mode
t
Bank 1 Status
Program mode
OE
Erase mode
Read mode
Read mode
Read mode
Read mode
Simultaneous Operation Table
“H”. The device can be read with standard access time (t
time) . When reading out data without changing addresses after power-
ACC
2
22
to A
and subsequent page read access (as long as the locations
to A
0
3
determining the specific word within that page. This is
constant and changing A
MBM29QM12DH
PACC
. Here again, CE selects the device
Autoselect mode
Bank 2 Status
Program mode
2
Erase mode
Read mode
Read mode
Read mode
Read mode
to A
0
within that page.
CE
CC
) from either of
± 0.3 V. Under
SS
± 0.3 V (CE
CC
active
-60
25