FW912 Micron Semiconductor Products, FW912 Datasheet - Page 10

• Manufacturer Part Number: FW912
• Description: Flash Memory Technology
• Manufacturer: Micron Semiconductor Products

STATUS REGISTER
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling OE# and CE# and reading the resulting
status code on I/Os DQ0–DQ7. The high-order I/Os
(DQ8–DQ15) are set to 00h internally, so only the low-
order I/Os (DQ0–DQ7) need to be interpreted. Address
lines select the status register pertinent to the selected
memory partition.
edge of ADV# or the rising (falling) edge of CLK when
ADV# is LOW during synchronous burst mode, or on
the falling edge of OE# or CE#, whichever occurs last.
Latching the data prevents errors from occurring if the
register input changes during status register monitor-
ing.
nal state of the WSM to the external microprocessor.
NOTE: 1. WA: Word address of memory location to be
4 Meg x 16 Async/Page/Burst Flash Memory
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
COMMAND
READ ARRAY
READ PROTECTION CONFIGURATION REGISTER
READ STATUS REGISTER
CLEAR STATUS REGISTER
READ QUERY
BLOCK ERASE SETUP
PROGRAM SETUP
ACCELERATED PROGRAMMING ALGORITHM (APA)
PROGRAM/ERASE SUSPEND
PROGRAM/ERASE RESUME – ERASE CONFIRM
LOCK BLOCK
UNLOCK BLOCK
LOCK DOWN BLOCK
CHECK BLOCK ERASE
PROTECTION REGISTER PROGRAM
PROTECTION REGISTER LOCK
SET READ CONFIGURATION REGISTER
The status register allows the user to determine
Register data is updated and latched on the falling
The status register provides a reading of the inter-
IA:
BA:
ID:
SRD: Data read from the status register
QA: Query code address
QD: Query code data
written, or read
Identification code address
Address within the block
Identification code data
Command Definitions
OPERATION ADDRESS
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
Table 4
ASYNC/PAGE/BURST FLASH MEMORY
10
FIRST BUS CYCLE
During periods when the WSM is active, the status reg-
ister can be polled to determine the WSM status. Table
8 defines the status register bits.
GRAM/ERASE operation, the data appearing on
DQ0–DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.
COMMAND STATE MACHINE
OPERATIONS
listed in Table 3. The 8-bit command code is input to
the device on DQ0–DQ7 (see Table 3 for CSM codes
and Table 4 for command definitions). During a PRO-
GRAM or ERASE cycle, the CSM informs the WSM that a
PROGRAM or ERASE cycle has been requested.
After monitoring the status register during a PRO-
The CSM decodes instructions for the commands
LPA
RCD
WA
WA
WA
QA
BA
BA
BA
BA
BA
BA
BA
BA
BA
PA
IA
WD: Data to be written at the location WA
PA:
PD:
LPA: Lock protection register address
RCD: Data to be written in the read configuration
X:
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
DATA
D0h
FFh
90h
70h
50h
98h
20h
40h
10h
B0h
60h
60h
60h
20h
C0h
C0h
60h
Protection register address
Data to be written at the location PA
register
“Don’t Care”
OPERATION ADDRESS
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
READ
READ
READ
SECOND BUS CYCLE
4 MEG x 16
LPA
RCD
WA
WA
QA
BA
BA
BA
BA
BA
PA
IA
X
©2002, Micron Technology, Inc.
ADVANCE
1
DATA
FFFDh
SRD
D0h
D0h
D1h
WD
WD
01h
2Fh
03h
QD
PD
ID