FW912 Micron Semiconductor Products, FW912 Datasheet - Page 27

• Manufacturer Part Number: FW912
• Description: Flash Memory Technology
• Manufacturer: Micron Semiconductor Products

READ-WHILE-WRITE/ERASE
CONCURRENCY
while erasing/writing to another bank. Once a bank
enters the WRITE/ERASE operation, the other bank
automatically enters read array mode. For example,
during a READ CONCURRENCY operation, if a PRO-
GRAM/ERASE command is issued in bank a, then bank
a changes to the read status mode and bank b defaults
to the read array mode. The device will read from bank
b if the latched address resides in bank b (see Figure
10). Similarly, if a PROGRAM/ERASE command is is-
sued in bank b, then bank b changes to read status
mode and bank a defaults to read array mode. When
returning to bank a, the device will read PROGRAM/
ERASE status if the latched address resides in bank a.
the status register after returning from a concurrent
read in the other bank.
ter, concurrent operation is not allowed on the top boot
device. Concurrent READ of the CFI or the chip protec-
tion register is only allowed when a PROGRAM or ERASE
operation is performed on bank b on the bottom boot
device. For a bottom boot device, reading of the CFI
table or the chip protection register is only allowed if
bank b is in read array mode. For a top boot device,
reading of the CFI table or the chip protection register
is only allowed if bank a is in read array mode.
READ CONFIGURATION REGISTER (RCR)
MODE
mand is a WRITE operation to the read configuration
register (RCR). It is a two-cycle command sequence.
Read configuration setup is written, followed by a sec-
ond write that specifies the data to be written to the
read configuration register. The data is placed on the
address bus A0–A15, and it is latched on the rising edge
of ADV#, CE#, or WE#, whichever occurs first. The read
configuration provides the read mode (burst, synchro-
nous, or asynchronous), burst order, latency counter,
and burst length. After executing this command, the
device returns to read array mode.
4 Meg x 16 Async/Page/Burst Flash Memory
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
It is possible for the device to read from one bank
A correct bank address must be specified to read
When reading the CFI or the chip protection regis-
The SET READ CONFIGURATION REGISTER com-
ASYNC/PAGE/BURST FLASH MEMORY
27
READ CONFIGURATION
asynchronous, synchronous burst mode, and page
mode. The bit RCR15 (see Table 9) in the read configu-
ration register sets the read configuration. Asynchro-
nous random mode is the default read mode.
ter support asynchronous and single synchronous
READ operations only.
Bank a
1 - Erasing/writing to bank a
2 - Erasing in bank a can be
3 - After the WRITE in that block
1 - Reading bank a
The device supports three read configurations:
At power-up, the RCR is set to BFCFh.
Status registers and the device identification regis-
suspended, and a WRITE to
another block in bank a
can be initiated.
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
READ-While-WRITE Concurrency
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 10
Bank b
1 - Reading from bank b
1 - Erasing/writing to bank b
2 - Erasing in bank b can be
3 - After the WRITE in that block
suspended, and a WRITE to
another block in bank b
can be initiated.
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
4 MEG x 16
©2002, Micron Technology, Inc.
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