FW912 Micron Semiconductor Products, FW912 Datasheet - Page 29

• Manufacturer Part Number: FW912
• Description: Flash Memory Technology
• Manufacturer: Micron Semiconductor Products

LATENCY COUNTER
that must elapse after ADV# is set active before data
will be available. This value depends on the input clock
frequency. See Table 10 for the specific input clock
frequency configuration code. Also, see Figure 11 for
the timing diagrams pertinent to codes 2, 3, and 4.
ADV#, active asynchronous access, and system strobe
for different latency counter codes.
HOLD DATA OUTPUT CONFIGURATION
how many clocks data will be held valid. (See Figure
12.)
4 Meg x 16 Async/Page/Burst Flash Memory
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
The latency counter provides the number of clocks
Table 10 illustrates the data output latency from
The hold data output configuration specifies for
DQ0–DQ15
DQ0–DQ15
A0–A20
ADV#
CLK
V
V
V
V
V
V
V
V
V
V
O L
O L
OH
OH
IH
IH
IH
IL
IL
IL
1 CLK
2 CLK
Hold
Data
Hold
Data
ADDRESS
VALID
DQ0–DQ15
DQ0–DQ15
Hold Data Output Configuration
Code 3
Code 4
CLK
Latency Counter
Figure 11
Figure 12
OUTPUT
VALID
ASYNC/PAGE/BURST FLASH MEMORY
29
OUTPUT
VALID
WAIT# CONFIGURATION
of the WAIT# output signal. The WAIT# signal can be
active during output delay or one data cycle before
delay, when continuous burst length is enabled. WAIT#
= 1 indicates valid data when RCR10 = 0. WAIT# = 0
indicates invalid data when RCR10 = 0. The setting of
WAIT# before or during the delay (RCR8) will depend
on the system and CPU characteristic. If RCR3 = 1 (no
wrap mode), then WAIT# can also be enabled in a four-
or eight-word burst if the no-wrap burst crosses the
first eight-word boundary.
OUTPUT
VALID
The wait configuration bit, RCR8, sets the behavior
OUTPUT
VALID
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OUTPUT
VALID
OUTPUT
OUTPUT
VALID
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
OUTPUT
VALID
VALID
4 MEG x 16
UNDEFINED
OUTPUT
OUTPUT
VALID
VALID
©2002, Micron Technology, Inc.
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