CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 10

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
1.5.2
1999 Consumer Microcircuits Limited
On reset, the coefficient RAMs are loaded with default values which provide the required response to
meet the needs of a TETRA baseband system. In the default modes the dynamic range of arithmetic
units are sufficient for all normal input data levels without causing overflows. Each filter has an odd
number of default coefficients, which are symmetrical, giving a linear phase response.
coefficients may be overwritten to adapt to other systems or compensate for deficiencies outside the
device. However the user is then responsible for ensuring that user supplied values do not cause
arithmetic overflows to occur within an accumulation cycle. Overflow logic within each filter can detect
such events and cause interrupts to be generated under user control.
The data RAMs store the filter input data samples and operate upon these values to provide the
general FIR transfer function:
When a filter is de-activated, coefficient RAMs retain their state, while the data RAMs are reset to
zero. This ensures that the filters start from a quiescent state and prevents filter “memory” from a
previous data frame. Asserting the N_RESET pin will cause all programmable filter coefficients to
return to default values. Alternatively, the Tx and Rx path filter coefficients may be reset independently
from each other by use of a control bit. The data RAMs, unlike the coefficient RAMs, are not directly
accessible to the user.
Read or write operations to the coefficient RAMs can be performed by accessing the base address,
which points to the MSB register of the first coefficient A1. This should be followed by a LSB register
access which will auto-index the internal RAM address pointer to A2. Successive operations will
continue to auto-index the RAM address pointer until A(FL) is reached. A further access after this
point leads to a reserved location A0 which should not be altered. Continuing operations beyond this
point returns the pointer to A1 again.
All filters, except the 79-tap Tx, allow access to the complete coefficient set, although the default
values are symmetrical about
functions should this be required.
All filters can be effectively by-passed by setting any single coefficient to normalised unity ( 2
Tx and 2
internal group delay, thus this feature should be used with care. For example, the Tx ramping feature
has a built in delay which defaults to the expected group delay for the Tx filter path. Ramp delay may
be bypassed, if required, by setting the appropriate bit in the BISTControl Register. The default group
delay can be retained by choosing the central coefficient as “unity”.
The 79-tap filter has only one half of the coefficient RAM available, so can only implement symmetrical
(linear phase) filter responses. Thus, when accessing this filter only locations A1-A40 are valid. In
Programmable FIR Filter Architecture
Within both the transmit and receive data path a common FIR filter architecture for the implementation
of the filtering requirements is employed. The filters use a small local static RAM for efficient data and
coefficient storage during filter operations, together with a dedicated hardware multiplier and
accumulator for each filter.
y(k)
15
-1 in Rx) and all others to zero. The chosen position of the “unity” coefficient will vary the
n FL
n 1
A D
n (n k)
.
(FL+1)/2. This will enable users to realise non-symmetrical filter
where:
10
FL
D
A
(n - k)
n
is the filter tap length
is the nth filter coefficient
is the data sample supplied to the
filter n-k samples previously
CMX980A
D/980A/3
11
-1 in the
These