CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 12

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
1.5.3.8 Symbol Clock Phase Adjustment
1.5.3.9 Direct Write to Tx 79-tap Filter Input
1.5.3.10 Test Access to DAC Input
1999 Consumer Microcircuits Limited
other systems where the modulator and filter blocks are not required. By operating the serial port at
the high serial clock rate and without a frame gap, it is possible to provide only half of the normal bit
rate for two channels, thus data can be provided at MCLK/64 for a single channel or MCLK/128 for
both channels. The user should provide the appropriate data at the required sample rate (MCLK/64 or
MCLK/128) via the serial interface, which will be transferred to the DAC logic at the next internal
sample clock after the data is written to the register. Write operations to the upper and lower byte
register and I and Q channels must be synchronised in phase by the user to the sample clock strobe.
This is to avoid splitting the I and Q channel or upper and lower bytes into different samples. The
phase of the sample clock can be determined by allowing the Symbol Clock ( which is in phase with
the internal sample clock but 1/8 of the rate) to appear on the N_IRQ pin.
Note that data input at this point will have to be pre-filtered to compensate for the reconstruction filter
droop (approximately 2dBs at MCLK/1024), which is normally compensated by the internal FIR default
coefficients. In addition, data input at a
MCLK/128, which will be reduced to about 65dBs below the wanted signal by the reconstruction filter.
There is some scope to improve this by enhancing the recommended single pole filter stage on the Tx
incremented by the value TxRampUpInc until the count of 2047 (1.0) is reached, or decremented by
the value in TxRampDnDec until zero is reached.
In linear mode, this value (RCR) is used directly to provide the envelope amplitude, whilst in non-linear
mode it is input to a look-up table of the sigmoidal function, which in turn provides the envelope
amplitude. Ramping begins from zero when
TxRampUp bit in the TxData Register set and continues in increments of TxRampUpInc until the set
gain level (see Section 1.5.3.3) is reached. To begin the ramp down phase of a transmit burst the user
writes post-amble data with the TxRampUp bit cleared then the RCR decrements by an amount
TxRampDnDec until the result is less than or equal to zero, whereupon the gain is set to zero. Internal
flag registers are available to indicate to the user that ramp down is complete.
The TxRampUpInc and TxRampDnDec Registers are both 9-bit words input via the serial interface
prior to the start of a transmission; this gives programmable ramping rates from 0.125 to 64 symbol-
times.
In order to comply with the requirement to maintain the phase error between the Mobile Station (MS)
and Base Station (BS) symbol clock to less than ñ 1/4 symbol time, a mechanism to allow phase
adjustment of the CMX980A symbol clock is provided.
This phase adjustment is achieved by writing a command to the SymClkPhase Register, which allows
adjustment in steps of ñ 1/4 or ñ 1/8 symbol times. It is intended that the user determines the symbol
clock phase of the BS after clock recovery has been performed on the received data. Then, allowing
for the fixed Tx path delay, the CMX980A phase can be advanced or retarded until it is within the
specified error limit. The internal symbol clock phase can be accessed by allowing the symbol clock
reference signal to appear on the N_IRQ pin, or alternatively using the I/Q identification mode (see
Section 1.5.7.3) which places the symbol clock in the Rx I channel LSB. Thus via hardware or
software means the internal Tx symbol clock reference time can be determined and the phase with
respect to the BS adjusted.
A mechanism to allow direct write to the I and Q Tx 79-tap filter inputs at the symbol rate is provided
for use in systems where a different modulation scheme is to be employed. See Section 1.5.7.4 for
further details.
A mechanism to allow read and write access to DAC input data is provided for use in testing or in
12
MCLK/128 sample rate will have a sinx/x alias around
the user applies valid transmission data with the
CMX980A
D/980A/3