CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 21
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CMX980AL7
Manufacturer Part Number
CMX980AL7
Description
TETRA Baseband Processor
Manufacturer
CML Microcircuits
Datasheet
1.CMX980AL7.pdf
(108 pages)
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TETRA Baseband Processor
1.5.8
1999 Consumer Microcircuits Limited
Register Description
This section describes in detail each of the registers and access points addressed by the Command
Control Serial Word.
Key to Register Map
Each section that follows describes in detail the operation and use of each of the registers in the
device. The registers are split into their functional groups, grouping associated registers together.
Each section consists of a Title, an Address, a Function Reference Field, a Description, and a Bit
Specification.
The Function Reference Field describes the overall access available to this section (RW/W/R, where
R = Read and W = Write).
The Bit Specification describes the function of each individual bit, or a range of bits within a register.
There is a separate line for each distinct field of bits. The State column indicates the action available
to each group of bits (RW/W/R). Address and data format illustrations show the bit positions in
multiple-byte transfers. “R” indicates a reserved bit, which should be set to logic zero when writing.
Its value is undefined when read. “X” indicates a don’t know/don’t care state.
Register Reset State
All I/O access points (both read and write) are reset to logic zero on taking N_RESET Low, except
where explicitly shown in this document. The reset state of status bits will depend on the level of the
status signal being monitored.
N_RESET Low.
Other registers (both read and write) are not affected by taking
21
CMX980A
D/980A/3
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