CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 87

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
1.6.4.2 Rx Path Details
1999 Consumer Microcircuits Limited
there are additional sources of attenuation or phase distortion, these can be catered for either by
designing a new pre-emphasis filter which incorporates gain to compensate for the attenuation in the
above table, or by designing another compensating filter and cascading with the filter described here.
Both approaches are essentially equivalent.
The I and Q Rx data paths are nominally identical and consist of the following elements:
The passband attenuation caused by the Rx AAF and decimation filters is compensated in the default
filter coefficients by convolving the required FIR response with a 15-tap pre-emphasis FIR filter. It
approximately cancels the filter attenuation up to a frequency of 10kHz. This pre-emphasis FIR filter
will track with the MCLK frequency, unlike the Rx AAF, but performance should be adequate for MCLK
frequencies between 7MHz and 12MHz. The user is free to alter the external RC filter and/or to
bypass the two on-chip poles of the AAF. In either case, the compensation FIR filter may require
adjustment. In the event of a user designing their own Rx AAF, it is suggested that close attention is
paid to the effect of component tolerances.
Two example sets of coefficients for this filter, for MCLK frequencies of 9.216MHz and 8.192MHz, are
given below. These assume that external components R2 and C2 are NOT changed from the default
values.
a) a continuous time anti-alias filter, which can be bypassed (2 poles at 100kHz, Q = 0.5
Note: The 32kHz pole is responsible for around 60% of the passband attenuation. The two
on-chip poles attenuate by approximately 0.1dB at 10kHz (equivalent to MCLK/922 for
MCLK=9.216MHz), while the decimation filter supplies 0.2dB at this frequency. Only the
decimation filter attenuation will track with MCLK, while the other poles will remain fixed
(subject to component tolerances). There is an 800ns variation in nominal group delay of this
decimation filter up to 10kHz. This could be compensated in the FIR coefficients if considered
significant.
b) a sigma delta ADC and decimation filter
c) a gain/offset adjustment block
d) a pair of programmable FIR filters (both 63-tap)
MCLK=9.216MHz
-0.00113692
-0.00227383
-0.00568459
-0.00909534
-0.0147799
-0.0193276
-0.0227383
1.16307
-0.0227383
-0.0193276
-0.0147799
-0.00909534
-0.00568459
-0.00227383
-0.00113692
on-chip and 1 pole at 32kHz off chip), with the following characteristic:
MCLK/Freq
Attenuation (dB)
MCLK=8.192MHz
-0.00112409
-0.00449636
-0.00899271
-0.0134891
-0.0191095
-0.0224818
-0.0224818
-0.0191095
-0.0134891
-0.00899271
-0.00449636
-0.00112409
0
1.14994
0
0
0
87
4608
0.03
2304
0.13
1536
0.29
1152
0.52
920
0.77
CMX980A
D/980A/3