CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 26

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
Title:
Address:
Function:
Description:
7:6
Bit
5
4
3
2
1
1999 Consumer Microcircuits Limited
PageAddress
n_SlowDown
SRamIoRdInc
SRamloEn
CoeffRamIoRdInc
CoeffRamloEn
ConfigCtrl2
Configuration Control register
$0x01
RW
General configuration bits, together with operational control signal bits.
Name
Data
Low
High
High
High
High
Active State
RW
RW
RW
RW
RW
RW
Page address field. All registers except ConfigCtrl1 and
ConfigCtrl2 use these bits to decode their actual address.
Reset defaults to page 0. The page address field applies to
all further commands, until a different page address is
selected.
When active, this bit reduces the slew rate of digital outputs.
This reduces power consumption, ground bounce and
reflection problems associated with fast edges on poorly
terminated lines. De-activation speeds up the digital outputs,
but increases power consumption, ground bounce and
reflection problems. It is anticipated that the latter mode will
be used only in 3.3V systems.
This bit determines whether a read or write operation to the
Auxiliary SRAM will increment the address pointers. When
set active causes read operations to move the address
pointer on, this would therefore allow an efficient write then
read verify scheme to be used. When set inactive write
operations increment the address pointer.
When set active allows read/write access to the Auxiliary
SRAM. This bit should not be activated when the SRAM is
being accessed by the RamDac. When this bit is set active,
the first access to the SramData Register will access the first
SRAM address location. Subsequent read or write accesses
will increment the address pointer to the next memory
location.
This bit determines whether a read or write operation to a
coefficient memory will increment the address pointers. When
set active the address pointer is incremented by any
coefficient ram read operation, thereby allowing a write then
read verification. When set inactive, write operations
increment the address pointer.
When set active allows read/write access to all the coefficient
memories. This bit is valid only when the Tx and Rx Data
paths are inactive. When this bit is set active, the first access
to any of the coefficient memories will access the first
coefficient location (A1). Subsequent read or write accesses
to any coefficient memory will increment the address pointers
for all the coefficient memories.
26
Function
CMX980A
D/980A/3