CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 91

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CMX980AL7

Manufacturer Part Number
CMX980AL7
Description
TETRA Baseband Processor
Manufacturer
CML Microcircuits
Datasheet

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TETRA Baseband Processor
1.6.8.5 Serial Interface Section
1999 Consumer Microcircuits Limited
A small power saving can be made if it is possible to run with a serial interface clock rate of MCLK/8.
This is accomplished by setting the DataRateHi bit in the ConfigCtrl1 Register inactive. Note that this
reduces the Rx output rate to four samples per symbol, although symbol timing can still be adjusted
using the RxSampleSel bit in the RxSetup1 Register and the vernier control in the RxSetup2
Register.
When running with a low serial interface clock rate, it is possible to invoke the serial interface clock
stop mode by using the AutoClkStopMode bit in the ClkStopCtrl Register. When active, this mode
will stop all serial interface activity if there is no activity on CmdFS for more than 4096 master clock
cycles. Note that this mode of operation stops the serial clock.
When the main serial interface activity involves loading symbols for transmission, the user can operate
in hardware handshake mode by using the TxHandshakeEn bit in the ConfigCtrl1 Register. Note that
this mode stops the serial clock if the transmit path is enabled and the transmit FIFO is full, thus the
use of the serial interface is less flexible.
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CMX980A
D/980A/3

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