CMX980AL7 CML Microcircuits, CMX980AL7 Datasheet - Page 11

• Manufacturer Part Number: CMX980AL7
• Description: TETRA Baseband Processor
• Manufacturer: CML Microcircuits

TETRA Baseband Processor
1.5.3
1.5.3.1 Modulator
1.5.3.2 Filters
1.5.3.3 Gain Multiplier
1.5.3.4 Offset Adjust
1.5.3.5 Sigma-Delta D-A Converters and Reconstruction Filters
1.5.3.6 Phase Pre-distortion
1.5.3.7 Ramping Output Amplitude
1999 Consumer Microcircuits Limited
addition, to bypass this filter, the central coefficient (A40) should be chosen as “unity”, since this is the
only unique coefficient.
Tx Data Path
The features described below give a high degree of flexibility for the user to compensate in the
baseband processing for non-ideal performance in the IF, RF and RF linear amplifier sections.
This takes the 2-bit symbols, performs a Gray Code conversion and uses a recursive adder to
generate a 3-bit code representing the 8 possible phase states. A look up table provides the digitally
encoded I and Q values for each phase state. The modulator function can be by-passed if required; in
this case the 3-bit code representing the 8 possible phase states which are passed to the look up
table is provided directly via the serial interface.
Digital filtering is applied to the data from the modulator by two programmable FIR filters. The first has
79-taps and provides stop band rejection and sampling correction. The second has 63-taps and
provides the primary Root Raised Cosine (RRC) shaping with Roll-off factor ( ) of 0.35, together with
correction for droop in the switched capacitor reconstruction filter. These FIR filters operate at eight
times the incoming symbol rate and are configured as two filters in cascade for each I and Q channel.
This feature allows user control of the signal amplitudes in the I and Q channels independently. The
multiplier provides a resolution of 11 bits; i.e. the gain is adjustable in steps of 1/2048 of maximum
level. Additional logic allows a mode of operation which will enable ramping up to the set signal level,
stay at this value while instructed by the user, then ramp back down to zero. The maximum value for
each channel, the ramping up rate and the ramping down rate are all programmable via the serial
interface.
Offset registers allow any offsets introduced in the analogue sections of the transmit path to be
corrected digitally via the serial interface. The offset adjust is independently applied to each of the I
and Q channels. The adjustment range is plus and minus full scale in each section with a resolution of
1 LSB. Thus care must be exercised by the user to avoid excessive offsets being applied to the
Sigma-Delta DAC.
The converters are designed to have low distortion and >80dB dynamic range. These 2nd order
converters operate at a frequency of 128 x symbol rate so as to over-sample the data at their inputs a
further 16 times. The reconstruction filters are 3rd order, switched capacitor, low pass filters designed
to work in conjunction with an external RC.
A further feature allows the user to compensate for a non-orthogonal carrier phase in the external
quadrature modulator by adding a programmable fraction of up to 1/8 of the filtered I and Q channel
signals to each other immediately prior to the DAC input.
A facility is provided to allow ramping of the outputs in two modes. When enabled by the user, the
signal from the gain multiplier stage is multiplied by an envelope value. The value in this register
increments or decrements at a rate programmed by the user, which is held in the TxRampUpInc and
TxRampDnDec Registers respectively.
The ramping envelope can be selected by the user to be linear or non-linear. In non-linear mode the
envelope function is sigmoidal, minimising spectrum spread whilst fast ramping is in operation. The
RCR is a 11-bit register (not user accessible), representing a value from 0 to 1.0, which can be
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CMX980A
D/980A/3